DJLXT971ALE.A4 Cortina Systems Inc, DJLXT971ALE.A4 Datasheet - Page 49

• Manufacturer Part Number: DJLXT971ALE.A4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT971ALE.A4

• Lead Free Status / RoHS Status: Not Compliant

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
5.7.3.3.4
Note:
5.7.3.4
5.8
Note:
5.8.1
5.8.2
5.8.3
Cortina Systems
Programmable Slew Rate Control
The LXT971A PHY device supports a programmable slew-rate mechanism whereby one
of four pre-selected slew rates can be used. (For details, see
Register - Address 30, Hex 1E, on page
designer to optimize the output waveform to match the characteristics of the magnetics.
For hardware control of the slew rate, use the TxSLEW pins.
Fiber PMD Sublayer
The LXT971A PHY provides an LVPECL interface for connection to an external 3.3 V or
5 V fiber-optic PHY. (The external PHY provides the PMD function for the optical
medium.) The LXT971A PHY uses a 125 Mbaud NRZI format for the fiber interface and
does not support 10BASE-FL applications.
10 Mbps Operation
The LXT971A PHY operates as a standard 10BASE-T PHY and LXT971A PHY supports
standard 10 Mbps functions. During 10BASE-T operation, the LXT971A PHY transmits
and receives Xilinks* Manchester-encoded data across the network link. When the MAC
is not actively transmitting data, the LXT971A PHY drives link pulses onto the line.
In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-
encoded signals received from the network are decoded by the LXT971A PHY and sent
across the MII to the MAC.
The LXT971A PHY does not support fiber connections at 10 Mbps.
10BASE-T Preamble Handling
The LXT971A PHY offers two options for preamble handling, selected by register bit 16.5.
10BASE-T Carrier Sense
For 10BASE-T links, CRS assertion is based on reception of valid preamble, and CRS de-
assertion is based on reception of an end-of-frame (EOF) marker. register bit 16.7 allows
CRS de-assertion to be synchronized with RX_DV de-assertion. For details, see
Configuration Register - Address 16, Hex 10, on page
10BASE-T Dribble Bits
The LXT971A PHY handles dribble bits in all modes. If one to four dribble bits are
received, the nibble is passed across the MII, padded with ones if necessary. If five to
seven dribble bits are received, the second nibble is not sent to the MII bus.
®
• In 10BASE-T mode when register bit 16.5 = 0, the LXT971A PHY strips the entire
• In 10BASE-T mode when register bit 16.5 = 1, the LXT971A PHY passes the
LXT971A Single-Port 10/100 Mbps PHY Transceiver
preamble off of received packets. CRS is asserted coincident with the start of the
preamble. RX_DV is held Low for the duration of the preamble. When RX_DV is
asserted, the very first two nibbles driven by the LXT971A PHY are the SFD “5D” hex
followed by the body of the packet.
preamble through the MII and asserts RX_DV and CRS simultaneously. (In
10BASE-T loopback, the LXT971A PHY loops back whatever the MAC transmits to it,
including the preamble.)
93.) The slew-rate mechanism allows the
86.
Table 62, Transmit Control
5.8 10 Mbps Operation
Table 56,
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