DS2152LN Maxim Integrated Products, DS2152LN Datasheet - Page 74

• Manufacturer Part Number: DS2152LN
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated Products

Specifications of DS2152LN

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 2.048 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current (max): 75 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14 TRANSMIT TRANSPARENCY
Each of the 24 T1 channels in the transmit direction of the DS2152 can be either forced to be transparent
or, in other words, can be forced to stop Bit 7 Stuffing and/or Robbed Signaling from overwriting the data
in the channels. Transparency can be invoked on a channel-by-channel basis by properly setting the
TTR1, TTR2, and TTR3 registers.
TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTER
(Address = 39 to 3B Hex)
Each of the bit positions in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represents a DS0
channel in the outgoing frame. When these bits are set to a 1, the corresponding channel is transparent (or
clear). If a DS0 is programmed to be clear, no robbed-bit signaling will be inserted nor will the channel
have Bit 7 stuffing performed. However, in the D4 framing mode, bit 2 will be overwritten by a 0 when a
Yellow Alarm is transmitted. Also, the user has the option to prevent the TTR registers from determining
which channels are to have Bit 7 stuffing performed. If the TCR2.0 and TCR1.3 bits are set to 1, then all
24 T1 channels will have Bit 7 stuffing performed on them regardless of how the TTR registers are
programmed. In this manner, the TTR registers are only affecting which channels are to have robbed-bit
signaling inserted into them. See
(MSB)
CH16
CH24
CH8
SYMBOL
CH24
CH1
CH15
CH23
CH7
POSITION
CH14
CH22
CH6
TTR3.7
TTR1.0
Figure 16-11
CH13
CH21
CH5
NAME AND DESCRIPTION
Transmit Transparency Registers.
0 = this DS0 channel is not transparent
1 = this DS0 channel is transparent
for more details.
CH12
CH20
CH4
74 of 97
CH11
CH19
CH3
CH10
CH18
CH2
(LSB)
CH17
CH1
CH9
TTR2 (3A)
TTR3 (3B)
TTR1 (39)