DS2152LN Maxim Integrated Products, DS2152LN Datasheet - Page 50

• Manufacturer Part Number: DS2152LN
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated Products

Specifications of DS2152LN

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 2.048 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current (max): 75 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9 PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK
The DS2152 can replace data on a channel-by-channel basis in both the transmit and receive directions.
The transmit direction is from the backplane to the T1 line and is covered in Section 9.1. The receive
direction is from the T1 line to the backplane and is covered in Section 9.2.
9.1 Transmit Side Code Generation
In the transmit direction there are two methods by which channel data from the backplane can be
overwritten with data generated by the DS2152. The first method, which is covered in Section 9.1.1, was
a feature contained in the original DS2151 while the second method, which is covered in Section 9.1.2, is
a new feature of the DS2152.
9.1.1 Simple Idle Code Insertion and Per-Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3) to determine which of the 24 T1
channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).
This method allows the same 8-bit code to be placed into any of the 24 T1 channels. If this method is
used, then the CCR4.0 control bit must be set to 0.
Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3) represents a DS0 channel in
the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). Robbed-bit signaling and Bit 7 stuffing will
occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit
Transparency Registers.
The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per-Channel
Loop-Back (PCLB). If the TIRFS control bit (CCR4.0) is set to 1, then the TIRs will determine which
channels (if any) from the backplane should be replaced with the data from the receive side or, in other
words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to
TSYNC.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address = 3C to 3E Hex)
(Also used for Per-Channel Loopback.)
Note: If CCR4.0 = 1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies that channel data is to be
sourced from the output of the receive side framer (i.e., Per-Channel Loopback; see
(MSB)
CH16
CH24
CH8
SYMBOL
CH24
CH1
CH15
CH23
CH7
POSITION
CH14
CH22
TIR3.7
TIR1.0
CH6
CH13
CH21
CH5
NAME AND DESCRIPTION
Transmit Idle Registers.
0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
50 of 97
CH12
CH20
CH4
CH11
CH19
CH3
Figure
1-1).
CH10
CH18
CH2
CH17
(LSB)
CH1
CH9
TIR2 (3D)
TIR1 (3C)
TIR3 (3E)