LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 33

Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch

LAN9312-NZW

Manufacturer Part Number
LAN9312-NZW
Description
Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
Manufacturer
SMSC
Type
Two Port Managed Ethernet Switchr
Datasheet

Specifications of LAN9312-NZW

Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Switches
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 Mbps, 100 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Supply Current (max)
186 mA, 295 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9312-NZW
Manufacturer:
Standard
Quantity:
143
Part Number:
LAN9312-NZW
Manufacturer:
Microchip Technology
Quantity:
10 000
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
PIN
67
68
69
70
Note: For more information on configuration straps, refer to
Note 3.6
PHY Address
MDIX Enable
MDIX Enable
LED Enable
Port 1 Auto-
Port 2 Auto-
NAME
Strap
Strap
Strap
Strap
page
in
Table
Configuration strap values are latched on power-on reset or nRST de-assertion.
Configuration strap pins are identified by an underlined symbol name. Some configuration
straps can be overridden by values from the EEPROM Loader. Refer to
"Configuration Straps," on page 40
40. Additional strap pins, which share functionality with the EEPROM pins, are described
3.5.
AUTO_MDIX_1
AUTO_MDIX_2
Table 3.6 Dedicated Configuration Strap Pins
PHY_ADDR_SEL
SYMBOL
LED_EN
DATASHEET
BUFFER
TYPE
(PU)
(PU)
(PU)
(PU)
IS
IS
IS
IS
33
for more information.
LED Enable Strap: Configures the default value
for the LED_EN bits in the
Register
LED/GPIO pins are configured as GPIOs. When
latched high, all 8 LED/GPIO pins are configured
as LEDs. See
PHY Address Select Strap: Configures the default
MII management address values for the PHYs
(Virtual, Port 1, and Port 2) as detailed in
7.1.1, "PHY Addressing," on page
See
Port 1 Auto-MDIX Enable Strap: Configures the
Auto-MDIX functionality on Port 1. When latched
low, Auto-MDIX is disabled. When latched high,
Auto-MDIX is enabled.
See
Port 2 Auto-MDIX Enable Strap: Configures the
Auto-MDIX functionality on Port 2. When latched
low, Auto-MDIX is disabled. When latched high,
Auto-MDIX is enabled.
See
0
1
Note
Note
Note
(LED_CFG). When latched low, all 8
3.6.
3.6.
3.6.
0
1
Section 4.2.4, "Configuration Straps," on
Note
DESCRIPTION
1
2
3.6.
2
3
LED Configuration
Revision 1.7 (06-29-10)
82.
Section 4.2.4,
Section

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