LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 105

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
8.4.3
SWITCH_CSR_DATA
AFTER READING...
VPHY_AN_EXP
RX Status FIFO
TX Status FIFO
RX Data FIFO
RX_DROP
Special Restrictions on Back-to-Back Read Cycles
There are also restrictions on specific back-to-back host read operations. These restrictions concern
reading specific registers after reading a resource that has side effects. In many cases there is a delay
between reading the LAN9312, and the subsequent indication of the expected change in the control
and status register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have
been established. These periods are specified in
specified period of time between read operations of specific combinations of resources. The wait period
is dependant upon the combination of registers being read.
Performing “dummy” reads of the
to guarantee that the minimum wait time restriction is met.
dummy reads that are required for back-to-back read operations. The number of BYTE_TEST reads
in this table is based on the minimum timing for T
the number of reads may be reduced as long as the total time is equal to, or greater than the time
specified in the table. Dummy reads of the BYTE_TEST register are not required as long as the
minimum time period is met.
Note 8.1
This timing applies only to the auto-increment and auto-decrement modes of Switch Fabric
CSR register access.
WAIT FOR THIS MANY
NANOSECONDS...
Table 8.2 Read After Read Timing Rules
135
135
135
180
45
45
Byte Order Test Register (BYTE_TEST)
DATASHEET
(ASSUMING T
105
OR PERFORM THIS MANY
READS OF BYTE_TEST…
Table
cyc
(45ns). For microprocessors with slower busses
8.2. The host processor is required to wait the
4
1
1
3
3
3
CYC
Table 8.2
OF 45NS)
below also shows the number of
register is a convenient way
BEFORE READING...
SWITCH_CSR_CMD
VPHY_AN_EXP
RX_FIFO_INF
RX_FIFO_INF
TX_FIFO_INF
Revision 1.7 (06-29-10)
RX_DROP
Note 8.1