LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 177

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.2.1.3
BITS
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
Software Interrupt Enable (SW_INT_EN)
Device Ready Enable (READY_EN)
1588 Interrupt Event Enable (1588_EVNT_EN)
Switch Engine Interrupt Event Enable (SWITCH_INT_EN)
Port 2 PHY Interrupt Event Enable (PHY_INT2_EN)
Port 1 PHY Interrupt Event Enable (PHY_INT1_EN)
TX Stopped Interrupt Enable (TXSTOP_INT_EN)
RX Stopped Interrupt Enable (RXSTOP_INT_EN)
RX Dropped Frame Counter Halfway Interrupt Enable
(RXDFH_INT_EN)
RESERVED
TX IOC Interrupt Enable (TIOC_INT_EN)
RX DMA Interrupt Enable (RXD_INT_EN)
GP Timer Interrupt Enable (GPT_INT_EN)
RESERVED
Power Management Event Interrupt Enable (PME_INT_EN)
TX Status FIFO Overflow Interrupt Enable (TXSO_EN)
Receive Watchdog Time-out Interrupt Enable (RWT_INT_EN)
Receiver Error Interrupt Enable (RXE_INT_EN)
Transmitter Error Interrupt Enable (TXE_INT_EN)
GPIO Interrupt Event Enable (GPIO_EN)
RESERVED - This bit must be written with 0b for proper operation.
TX Data FIFO Overrun Interrupt Enable (TDFO_EN)
TX Data FIFO Available Interrupt Enable (TDFA_EN)
TX Status FIFO Full Interrupt Enable (TSFF_EN)
TX Status FIFO Level Interrupt Enable (TSFL_EN)
RX Dropped Frame Interrupt Enable (RXDF_INT_EN)
Interrupt Enable Register (INT_EN)
This register contains the interrupt enables for the IRQ output pin. Writing 1 to any of the bits enables
the corresponding interrupt as a source for IRQ. Bits in the
will still reflect the status of the interrupt source regardless of whether the source is enabled as an
interrupt in this register (with the exception of SW_INT_EN). For descriptions of each interrupt, refer
to the
Interrupt Status Register (INT_STS)
Offset:
05Ch
DESCRIPTION
DATASHEET
177
bits, which mimic the layout of this register.
Size:
Interrupt Status Register (INT_STS)
32 bits
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
Revision 1.7 (06-29-10)
DEFAULT
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
-
-
register