LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 97

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
7.2.5.1
Auto-negotiation is started by the occurrence of any of the following events:
Note: Refer to
On detection of one of these events, the PHY begins auto-negotiation by transmitting bursts of Fast
Link Pulses (FLP). These are bursts of link pulses from the 10M TX Driver. They are shaped as Normal
Link Pulses and can pass uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst consists
of up to 33 pulses. The 17 odd-numbered pulses, which are always present, frame the FLP burst. The
16 even-numbered pulses, which may be present or absent, contain the data word being transmitted.
Presence of a data pulse represents a “1”, while absence represents a “0”.
The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE
802.3 clause 28. In summary, the PHY advertises 802.3 compliance in its selector field (the first 5 bits
of the Link Code Word). It advertises its technology ability according to the bits set in the
Auto-Negotiation Advertisement Register
There are 4 possible matches of the technology abilities. In the order of priority these are:
If the full capabilities of the PHY are advertised (100M, full-duplex), and if the link partner is capable
of 10M and 100M, then auto-negotiation selects 100M as the highest performance mode. If the link
partner is capable of half and full-duplex modes, then auto-negotiation selects full-duplex as the highest
performance mode.
Once a speed and duplex match has been determined, the link code words are repeated with the
acknowledge bit set. Any difference in the main content of the link code words at this time will cause
auto-negotiation to re-start. Auto-negotiation will also re-start if all of the required FLP bursts are not
received.
Writing the
Full Duplex
software control of the capabilities advertised by the PHY. Writing the
Advertisement Register (PHY_AN_ADV_x)
x PHY Basic Control Register
bit must be set before the new abilities will be advertised. Auto-negotiation can also be disabled via
software by clearing the
(PHY_BASIC_CONTROL_x).
PHY Pause Flow Control
The Port 1 & 2 PHYs are capable of generating and receiving pause flow control frames per the IEEE
802.3 specification. The PHYs advertised pause flow control abilities are set via the
Power-On Reset (POR)
Hardware reset (nRST)
PHY Software reset (via
Port x PHY Basic Control Register
PHY Power-down reset
PHY Link status down (the
(PHY_BASIC_STATUS_x)
Setting the
Negotiation (PHY_RST_AN)
Digital Reset (via the
Issuing an EEPROM Loader RELOAD command
100M Full Duplex (highest priority)
100M Half Duplex
10M Full Duplex
10M Half Duplex (lowest priority)
10BASE-T Half
bits of the
Port x PHY Basic Control Register
Section 4.2, "Resets," on page 42
Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)
Digital Reset (DIGITAL_RST)
Auto-Negotiation (PHY_AN)
Duplex,
(Section 7.2.9, "PHY Power-Down Modes," on page
Reset Control Register
is cleared)
(PHY_BASIC_CONTROL_x),
Link Status
bit high
DATASHEET
10BASE-T Full
(PHY_BASIC_CONTROL_x))
(PHY_AN_ADV_x).
97
bit of the
does not automatically re-start auto-negotiation. The
(PHY_BASIC_CONTROL_x),
for information on these and other system resets.
(RESET_CTL), or the
Duplex,
Port x PHY Basic Status Register
(Section 8.4, "EEPROM Loader," on page
bit of the
bit of the
100BASE-X Half
Restart Auto-Negotiation (PHY_RST_AN)
Reset Control Register
Port x PHY Basic Control Register
Port x PHY Auto-Negotiation
Reset (PHY_RST)
Duplex, and
100)
Restart Auto-
Revision 1.4 (07-07-10)
Symmetric Pause
(RESET_CTL))
100BASE-X
Port x PHY
bit of the
allows
113)
Port