LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 249

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
13.4.2.23
BITS
31:8
6:2
7
1
0
RESERVED
MAC Counter Test
When set, TX and RX counters that normally clear to 0 when read, will be
set to 7FFF_FFFCh when read with the exception of the
Receive Packet Length Count Register
MAC Transmit Packet Length Count Register
and
(MAC_RX_GOODPKTLEN_CNT_x)
7FFF_FF80h.
IFG Config
These bits control the transmit inter-frame gap.
IFG bit times = (IFG Config *4) + 12
Note:
TX Pad Enable
When set, packets shorter than 64 bytes are padded with zeros if needed
and a FCS is appended. Packets that are 60 bytes or less will become 64
bytes. Packets that are 61, 62, and 63 bytes will become 65, 66, and 67
bytes respectively.
TX Enable
When set, the transmit port is enabled. When cleared, the transmit port is
disabled.
Port x MAC Transmit Configuration Register (MAC_TX_CFG_x)
This read/write register configures the transmit packet parameters of the port.
Port x MAC Receive Good Packet Length Count Register
IFG Config values less than 15 are unsupported.
Register #:
Port0: 0440h
Port1: 0840h
Port2: 0C40h
DESCRIPTION
counters which will be set to
DATASHEET
(MAC_RX_PKTLEN_CNT_x),
249
(MAC_TX_PKTLEN_CNT_x),
Size:
Port x MAC
32 bits
Port x
TYPE
R/W
R/W
R/W
R/W
RO
Revision 1.4 (07-07-10)
DEFAULT
10101b
0b
1b
1b
-