LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 126

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.4 (07-07-10)
10.2.2
10.3
10.3.1
WRITE
READ
PREAMBLE
Write Sequence
In a write sequence, the host sends the 32-bit preamble, 2-bit start of frame, 2-bit op-code, 5-bit PHY
Address, 5-bit Register Address, 2-bit turn-around time, and finally the 16-bits of data. The MDIO pin
is three-stated throughout the write sequence.
The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD
transfer. No ordering requirement exists. The host may access either the low or high word first, as long
as the next write is performed to the opposite word. If a write to the same word is performed, the device
disregards the transfer.
Note: SMI writes must not be performed to unused register addresses.
The PHY Management Interface (PMI) is used to access the internal PHYs as well as the external
PHY on the MII pins (in MAC modes only). The PMI operates at 2.5MHz, and implements the IEEE
802.3 management protocol, providing read/write commands for PHY configuration.
A read or write is performed using the frame format shown in
transferred msb first. Data bytes are transferred little endian.
Note 10.4 The turn-around time (TA) is used to avoid bus contention during a read cycle. For a read,
Note 10.5 In the IDLE condition, the MDIO output is three-stated and pulled high externally.
The internal PHYs and optional external PHY (in MAC modes) are accessed via the
Interface Access Register (PMI_ACCESS)
(PMI_DATA). These registers allow read and write operations to all PHY registers. Refer to
13.2.5, "PHY Management Interface (PMI)," on page 167
EEPROM Loader PHY Register Access
The PMI is also used by the EEPROM Loader to load the PHY registers with various configuration
strap values. The
Interface Data Register (PMI_DATA)
of the EEPROM Loader. Refer to
information.
PHY Management Interface (PMI)
32 1’s
32 1’s
the external PHY drives the second bit of the turn-around time to 0, and then drives the
msb of the read data in the following cycle. For a write, the device drives the first bit of
the turnaround time to 1, the second bit of the turnaround time to 0, and then the msb of
the write data in the following clock cycle.
START
01
01
PHY Management Interface Access Register (PMI_ACCESS)
Table 10.2 MII Management Frame Format
CODE
OP
10
01
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
ADDRESS
AAAAA
AAAAA
PHY
DATASHEET
are also accessible as part of the Register Data burst sequence
Section 8.4, "EEPROM Loader," on page 113
126
REGISTER
ADDRESS
RRRRR
RRRRR
and
PHY Management Interface Data Register
AROUND
Note 10.4
for detailed information on these registers.
TURN-
TIME
Z0
10
Table
10.2. All addresses and data are
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
DATA
SMSC LAN9303/LAN9303i
and
PHY Management
PHY Management
for additional
Datasheet
Section
IDLE
Note
10.5
Z
Z