LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 148

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.4 (07-07-10)
13.2.3
13.2.3.1
BITS
31
EEPROM Controller Busy (EPC_BUSY)
When a 1 is written into this bit, the operation specified in the
EPC_COMMAND field of this register is performed at the specified
EEPROM address. This bit will remain set until the selected operation is
complete. In the case of a read, this indicates that the Host can read valid
data from the
E2P_DATA registers should not be modified until this bit is cleared. In the
case where a write is attempted and an EEPROM is not present, the
EPC_BUSY bit remains set until the
(EPC_TIMEOUT)
Note:
EEPROM
This section details the EEPROM related System CSR’s. These registers should only be used if an
EEPROM has been connected to the device. Refer to chapter
Controller," on page 107
EEPROM Command Register (E2P_CMD)
This read/write register is used to control the read and write operations of the serial EEPROM.
EPC_BUSY is set immediately following power-up, or pin reset, or
Digital Reset
finished loading, the EPC_BUSY bit is cleared. Refer to chapter
Section 8.4, "EEPROM Loader," on page 113
Offset:
EEPROM Data Register
bit is set. At this time the EPC_BUSY bit is cleared.
(DIGITAL_RST). After the EEPROM Loader has
for additional information.
1B4h
DESCRIPTION
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
EEPROM Controller Timeout
DATASHEET
(E2P_DATA). The E2P_CMD and
148
Size:
for more information.
32 bits
Section 8.3, "I2C Master EEPROM
TYPE
R/W
SMSC LAN9303/LAN9303i
SC
DEFAULT
Datasheet
0b