LAN9313I-NZW SMSC, LAN9313I-NZW Datasheet - Page 96

• Manufacturer Part Number: LAN9313I-NZW
• Description: Ethernet ICs Three Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Three Port Managed Ethernet Switchr

Specifications of LAN9313I-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 155 mA, 270 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.7 (06-29-10)
7.2.8
7.2.8.1
7.2.9
Auto-Negotiation LP Acknowledge
Link Down (Link Status Negated)
Auto-Negotiation Page Received
For a transmission, the switch fabric MAC drives the transmit data onto the internal MII TXD bus and
asserts TXEN to indicate valid data. The data is in the form of 4-bit wide data at a rate of 25MHz for
100BASE-TX, or 2.5MHz for 10BASE-T.
For reception, the 4-bit data nibbles are sent to the MII MAC Interface block. These data nibbles are
clocked to the controller at a rate of 25MHz for 100BASE-TX, or 2.5MHz for 10BASE-T. RXCLK is the
output clock for the internal MII bus. It is recovered from the received data to clock the RXD bus. If
there is no received signal, it is derived from the system reference clock.
PHY Management Control
The PHY Management Control block is responsible for the management functions of the PHY,
including register access and interrupt generation. A Serial Management Interface (SMI) is used to
support registers 0 through 6 as required by the IEEE 802.3 (Clause 22), as well as the vendor specific
registers allowed by the specification. The SMI interface consists of the MII Management Data (MDIO)
signal and the MII Management Clock (MDC) signal. These signals interface to the MDIO and MDC
pins of the LAN9313/LAN9313i (or the PMI block in I
to all PHY registers. Refer to
supported registers and register descriptions. Non-supported registers will be read as FFFFh.
PHY Interrupts
The PHY contains the ability to generate various interrupt events as described in
the
the interrupt, and clears the interrupt signal. The
(PHY_INTERRUPT_MASK_x)
block aggregates the enabled interrupts status into an internal signal which is sent to the System
Interrupt Controller and is reflected via the
the Port 1 PHY, and bit 27 (PHY_INT2) for the Port 2 PHY. For more information on the
LAN9313/LAN9313i interrupts, refer to
PHY Power-Down Modes
There are two power-down modes for the PHY:
Note: For more information on the various power management features of the LAN9313/LAN9313i,
Auto-Negotiation Complete
Parallel Detection Fault
INTERRUPT SOURCE
Remote Fault Detected
ENERGYON Activated
PHY General Power-Down
PHY Energy Detect Power-Down
Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x)
refer to
Section 4.3, "Power Management," on page
Table 7.3 PHY Interrupt Sources
Section 13.2.2, "Port 1 & 2 PHY Registers," on page 231
enables or disables each PHY interrupt. The PHY Management Control
DATASHEET
Chapter 5, "System Interrupts," on page
96
Interrupt Status Register (INT_STS)
PHY_INTERRUPT_SOURCE_x REGISTER BIT #
2
C and SPI modes of operation) and allow access
PHY_INTERRUPT_MASK_x &
Port x PHY Interrupt Mask Register
51.
Three Port 10/100 Managed Ethernet Switch with MII
7
6
5
4
3
2
1
SMSC LAN9313/LAN9313i
bit 26 (PHY_INT1) for
52.
shows the source of
Table
for a list of all
7.3. Reading
Datasheet