LAN9313I-NZW SMSC, LAN9313I-NZW Datasheet - Page 39

• Manufacturer Part Number: LAN9313I-NZW
• Description: Ethernet ICs Three Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Three Port Managed Ethernet Switchr

Specifications of LAN9313I-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 155 mA, 270 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
SMSC LAN9313/LAN9313i
77-79,
PIN
PIN
108
70
82
63
71
75
Note: Refer to
Note 3.14 The input buffers are enabled when configured as GPIO inputs only.
System Reset
Serial Clock
Serial Clock
Purpose I/O
SPI Slave
I
2
Interrupt
General
NAME
NAME
Output
C Slave
Test 1
Test 2
Input
Data
regarding the serial management configuration and functionality.
Section Chapter 8, "Serial Management," on page 101
Table 3.7 Serial Management Pins (continued)
GPIO[11:8]
SYMBOL
SYMBOL
TEST1
TEST2
nRST
SCK
SCL
IRQ
Table 3.8 Miscellaneous Pins
DATASHEET
BUFFER
BUFFER
IS/OD12/
Note 3.14
O8/OD8
TYPE
TYPE
(PU)
(PU)
(PU)
O12
IS
IS
AI
AI
IS
39
SPI Slave Serial Clock: In SPI slave mode, this
pin is the SPI clock input.
Note:
I
is the I
Note:
General Purpose I/O Data: These general
purpose signals are fully programmable as either
push-pull outputs, open-drain outputs, or Schmitt-
triggered inputs by writing the
Configuration Register (GPIO_CFG)
Purpose I/O Data & Direction Register
(GPIO_DATA_DIR). For more information, refer to
Chapter 12, "GPIO/LED Controller," on page
Note:
Interrupt Output: Interrupt request output. The
polarity, source and buffer type of this signal is
programmable via the
Register
Chapter 5, "System Interrupts," on page
System Reset Input: This active low signal allows
external hardware to reset the LAN9313/LAN9313i.
The LAN9313/LAN9313i also contains an internal
power-on reset circuit. Thus, this signal may be left
unconnected if an external hardware reset is not
needed. When used, this signal must adhere to the
reset timing requirements as detailed in
14.5.2, "Reset and Configuration Strap Timing," on
page
Test 1: This pin must be tied to VDD33IO for
proper operation.
Test 2: This pin must be tied to VDD33IO for
proper operation.
2
C Slave Serial Clock: In I
389.
2
C clock input.
(IRQ_CFG). For more information, refer to
In SMI slave and unmanaged modes, this
pin is unused and pulled-up internally.
In SMI slave and unmanaged modes, this
pin is unused and pulled-up internally.
The remaining GPIO[7:0] pins share
functionality with the LED output pins, as
described in
DESCRIPTION
DESCRIPTION
Table 3.1
Interrupt Configuration
for additional information
2
C slave mode, this pin
General Purpose I/O
Revision 1.7 (06-29-10)
and
Table
and
52.
Section
General
3.2.
142.