LAN9313I-NZW SMSC, LAN9313I-NZW Datasheet - Page 105

• Manufacturer Part Number: LAN9313I-NZW
• Description: Ethernet ICs Three Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Three Port Managed Ethernet Switchr

Specifications of LAN9313I-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 155 mA, 270 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
SMSC LAN9313/LAN9313i
8.2.2.2
S 1 0 1 0
Control Byte
Chip / Block
EE_SDA
Select Bits
EE_SCL
Single Byte Addressing
A
1
0
Figure 8.2
I
The I
by the address byte or bytes. The control byte is preceded by a start condition. The control byte and
address byte(s) are each acknowledged by the EEPROM slave. If the EEPROM slave fails to send an
acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit of the
Register (E2P_CMD)
The control byte consists of a 4-bit control code, 3-bits of chip/block select and one direction bit. The
control code is 1010b. For single byte addressing EEPROMs, the chip/block select bits are used for
address bits 10, 9, and 8. For double byte addressing EEPROMs, the chip/block select bits are set
low. The direction bit is set low to indicate the address is being written.
Figure 8.3
2
A
9
Start Condition
C EEPROM Device Addressing
A
8
2
0
R/~W
C EEPROM is addressed for a read or write operation by first sending a control byte followed
S
A
C
K
A
7
displays the various bus states of a typical I
illustrates typical I
A
6
Address Byte
A
5
change
data
can
A
4
A
3
is set.
A
2
Data Valid
or Ack
A
Figure 8.3 I
stable
1
data
A
0
2
A
C
K
C EEPROM addressing bit order for single and double byte addressing.
change
Figure 8.2 I
data
can
DATASHEET
S 1 0 1 0
2
C EEPROM Addressing
Condition
Control Byte
Re-Start
105
Chip / Block
Select Bits
Sr
2
C Cycle
0 0 0
change
data
0
can
R/~W
2
C cycle.
A
C
K
Double Byte Addressing
A
1
5
Data Valid
A
or Ack
1
4
Address High
stable
data
A
1
3
Byte
A
1
2
A
1
1
change
A
1
0
data
can
A
9
A
8
A
C
K
A
7
EEPROM Command
Stop Condition
Revision 1.7 (06-29-10)
A
6
Address Low
A
5
P
Byte
A
4
A
3
A
2
A
1
A
0
C
A
K