DS21455 Maxim Integrated Products, DS21455 Datasheet - Page 85

• Manufacturer Part Number: DS21455
• Description: Network Controller & Processor ICs Quad E1-T1-J1 Single -Chip Transceiver (S
• Manufacturer: Maxim Integrated Products

Specifications of DS21455

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

15. ERROR COUNT REGISTERS
The DS21455/DS21458 contain four counters that are used to accumulate line coding errors, path errors,
and synchronization errors. Counter update options include one second boundaries, 42ms (T1 mode
only), 62ms (E1 mode only) or manually. See Error Counter Configuration Register (ERCNT). When
updated automatically, the user can use the interrupt from the timer to determine when to read these
registers. All four counters will saturate at their respective maximum counts and they will not rollover
(Note: Only the line-code violation count register has the potential to overflow but the bit error would
have to exceed 10E-2 before this would occur).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/T1 Line Code Violation Count Register Function Select (LCVCRF).
Bit 1/Multiframe Out-of-Sync Count Register Function Select (MOSCRF).
Bit 2/PCVCR Fs-Bit Error Report Enable (FSBE).
Bit 3/E1 Line Code Violation Count Register Function Select (VCRFS).
Bit 4/Error Accumulation Mode Select (EAMS).
Bit 5/Error Counter Update Select (ECUS).
T1 Mode: 0 = Update error counters once a second
E1 Mode: 0 = Update error counters once a second
Bit 6/Manual Error Counter Update (MECU). When enabled by ERCNT.4, the changing of this bit from a zero to a one
allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The user must wait a
minimum of 1.5 RCLK clock periods before reading the error count registers to allow for proper update.
Bit 7/Unused, must be set to zero for proper operation.
0 = do not count excessive zeros
1 = count excessive zeros
0 = count errors in the framing bit position
1 = count the number of multiframes out of sync
0 = do not report bit errors in Fs-bit position; only Ft-bit position
1 = report bit errors in Fs-bit position as well as Ft-bit position
0 = count Bipolar Violations (BPVs)
1 = count Code Violations (CVs)
0 = ERCNT.5 determines accumulation time
1 = ERCNT.6 determines accumulation time
1 = Update error counters every 42ms (333 frames)
1 = Update error counters every 62.5ms (500 frames)
—
7
0
MECU
ERCNT
Error Counter Configuration Register
41h
6
0
ECUS
5
0
EAMS
4
0
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VCRFS
3
0
FSBE
2
0
MOSCRF
1
0
LCVCRF
0
0