DS21455 Maxim Integrated Products, DS21455 Datasheet - Page 49

• Manufacturer Part Number: DS21455
• Description: Network Controller & Processor ICs Quad E1-T1-J1 Single -Chip Transceiver (S
• Manufacturer: Maxim Integrated Products

Specifications of DS21455

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

8.1 Power-Up Sequence
The DS21455/DS21458 contain an on-chip power-up reset function, which automatically clears the
writeable register space immediately after power is supplied to the device. The user can issue a chip reset
at any time. Issuing a reset will disrupt traffic until the device is reprogrammed. The reset can be issued
through hardware using the TSTRST pin or through software using the SFTRST function in the master
mode register. The LIRST (LIC2.6) should be toggled from zero to one to reset the line interface
circuitry. (It will take the DS21455/DS21458 about 40ms to recover from the LIRST bit being toggled.)
Finally, after the TSYSCLK and RSYSCLK inputs are stable, the receive and transmit elastic stores
should be reset (this step can be skipped if the elastic stores are disabled).
8.1.1 Master Mode Register
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Software Issued Reset (SFTRST).
A 0 to 1 transition causes the register space to be cleared. A reset clears all configuration and status registers. The bit
automatically clears itself when the reset has completed.
Bit 1/Operating Mode (T1/E1).
Used to select the operating mode of the framer/formatter (digital) portion of the DS21455. The operating mode of the LIU
must also be programmed.
Bits 2, 3/Test Mode Bits (TEST0, TEST1).
Test modes are used to force the output pins of the DS21455 into known states. This can facilitate the checkout of assemblies
during the manufacturing process and also be used to isolate devices from shared buses.
Bits 4–7/Unused, must be set to zero for proper operation.
TEST1
0
0
1
1
0 = T1 operation
1 = E1 operation
TEST0
—
7
0
0
1
0
1
Operate normally
Force all output pins low (including all I/O pins except parallel port pins)
Force all output pins high (including all I/O pins except parallel port pins)
Force all output pins into tri-state (including all I/O pins and parallel port pins)
—
MSTRREG
Master Mode Register
00h
6
0
—
5
0
EFFECT ON OUTPUT PINS
—
4
0
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TEST1
3
0
TEST0
2
0
T1/E1
1
0
SFTRST
0
0