DS21455 Maxim Integrated Products, DS21455 Datasheet - Page 186

• Manufacturer Part Number: DS21455
• Description: Network Controller & Processor ICs Quad E1-T1-J1 Single -Chip Transceiver (S
• Manufacturer: Maxim Integrated Products

Specifications of DS21455

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

27. BERT FUNCTION
The BERT (Bit Error-Rate Tester) block can generate and detect both pseudorandom and repeating-bit
patterns. It is used to test and stress data-communication links.
The BERT block can generate and detect the following patterns:
The BERT function is assigned on a per-channel basis for both the transmitter and receiver. This is
accomplished by using the special per-channel function. Using this function, the BERT pattern can be
transmitted and/or received in single or across multiple DS0s, contiguous or broken. Transmit and receive
bandwidth assignments are independent of each other.
The BERT receiver has a 32-bit bit counter and a 24-bit error counter. The BERT receiver will report
three events: a change in receive-synchronizer status, a bit error detection, and if either the bit counter or
the error counter overflows. Each of these events can be masked within the BERT function via the BERT
control register 1 (BC1). If the software detects that the BERT has reported an event, then the software
must read the BERT information register (BIR) to determine which event(s) has occurred. To activate the
BERT block, the host must configure the BERT multiplexer via the BIC register.
SR9 contains the status information on the BERT function. The host can be alerted when there is a
change of state of the BERT via this register. A major change of state is defined as either a change in the
receive synchronization (i.e., the BERT has gone into or out of receive synchronization), a bit error has
been detected, or an overflow has occurred in either the bit counter or the error counter. The host must
read SR9 to determine the change of state.
The pseudorandom patterns 2E7, 2E11, 2E15, and QR
A repetitive pattern from 1 to 32 bits in length
Alternating (16-bit) words that flip every 1 to 256 words
Daly pattern
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