DS21455 Maxim Integrated Products, DS21455 Datasheet - Page 117

• Manufacturer Part Number: DS21455
• Description: Network Controller & Processor ICs Quad E1-T1-J1 Single -Chip Transceiver (S
• Manufacturer: Maxim Integrated Products

Specifications of DS21455

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive Elastic Store Enable (RESE).
Bit 1/Receive Elastic Store Minimum Delay Mode (RESMDM). See the Minimum Delay Mode section for details.
Bit 2/Receive Elastic Store Reset (RESR). Setting this bit from a zero to a one forces the read and write pointers into
opposite frames, maximizing the delay through the receive elastic store. Should be toggled after RSYSCLK has been applied
and is stable. See the Elastic Stores Initialization section for details. Do not leave this bit set HIGH.
Bit 3/Receive Elastic Store Align (RESALGN). Setting this bit from a zero to a one will force the receive elastic store’s
write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is already greater
or equal to half a frame. If pointer separation is less than half a frame, the command will be executed and the data will be
disrupted. Should be toggled after RSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent
align. See the Elastic Stores Initialization section for details.
Bit 4/Transmit Elastic Store Enable (TESE).
Bit 5/Transmit Elastic Store Minimum Delay Mode (TESMDM). See the Minimum Delay Mode section for details.
Bit 6/Transmit Elastic Store Reset (TESR). Setting this bit from a zero to a one forces the read and write pointers into
opposite frames, maximizing the delay through the transmit elastic store. Transmit data is lost during the reset. Should be
toggled after TSYSCLK has been applied and is stable. See the Elastic Stores Initialization section for details. Do not leave
this bit set HIGH.
Bit 7/Transmit Elastic Store Align (TESALGN). Setting this bit from a zero to a one will force the transmit elastic store’s
write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is already greater
or equal to half a frame. If pointer separation is less than half a frame, the command will be executed and the data will be
disrupted. Should be toggled after TSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent
align. See the Elastic Stores Initialization section for details.
0 = elastic store is bypassed
1 = elastic store is enabled
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32-bit depth
0 = elastic store is bypassed
1 = elastic store is enabled
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32-bit depth
TESALGN
7
0
ESCR
Elastic Store Control Register
4Fh
TESR
6
0
TESMDM
5
0
TESE
117 of 270
4
0
RESALGN
3
0
RESR
2
0
RESMDM
1
0
RESE
0
0