DS21455 Maxim Integrated Products, DS21455 Datasheet - Page 142

• Manufacturer Part Number: DS21455
• Description: Network Controller & Processor ICs Quad E1-T1-J1 Single -Chip Transceiver (S
• Manufacturer: Maxim Integrated Products

Specifications of DS21455

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

Table 24-1. HDLC Controller Registers
H1TC, HDLC #1 Transmit Control Register
H2TC, HDLC #2 Transmit Control Register
H1RC, HDLC #1 Receive Control Register
H2RC, HDLC #2 Receive Control Register
H1FC, HDLC #1 FIFO Control Register
H2FC, HDLC #2 FIFO Control Register
SR6, HDLC #1 Status Register
SR7, HDLC #2 Status Register
IMR6, HDLC #1 Interrupt Mask Register
IMR7, HDLC #2 Interrupt Mask Register
INFO4, HDLC #1 & #2 Information Register
INFO5, HDLC #1 Information Register
INFO6, HDLC #2 Information Register
H1RPBA, HDLC #1 Receive Packet Bytes Available
Register
H2RPBA, HDLC #2 Receive Packet Bytes Available
Register
H1TFBA, HDLC #1 Transmit FIFO Buffer Available
Register
H2TFBA, HDLC #2 Transmit FIFO Buffer Available
Register
H1RCS1, H1RCS2, H1RCS3, H1RCS4, HDLC #1
Receive Channel Select Registers
H2RCS1, H2RCS2, H2RCS3, H2RCS4, HDLC #2
Receive Channel Select Registers
H1RTSBS, HDLC #1 Receive TS/Sa Bit Select Register
H2RTSBS, HDLC #2 Receive TS/Sa Bit Select Register
H1TCS1, H1TCS2, H1TCS3, H1TCS4, HDLC #1
Transmit Channel Select Registers
H2TCS1, H2TCS2, H2TCS3, H2TCS4, HDLC #2
Transmit Channel Select Registers
H1TTSBS, HDLC # 1 Transmit TS/Sa Bit Select Register
H2TTSBS, HDLC # 2 Transmit TS/Sa Bit Select Register
H1RF, HDLC #1 Receive FIFO Register
H2RF, HDLC #2 Receive FIFO Register
H1TF, HDLC #1 Transmit FIFO Register
H2TF, HDLC #2 Transmit FIFO Register
NAME
CONTROL/CONFIGURATION
STATUS/INFORMATION
MAPPING
142 of 270
FIFOs
General control over the transmit HDLC controllers
General control over the receive HDLC controllers
Sets high watermark for receiver and low watermark for
transmitter
Key status information for both transmit and receive
directions
Selects which bits in Status Registers (SR7 and SR8) will
cause interrupts
Information on HDLC controller
Indicates the number of bytes that can be read from the
receive FIFO
Indicates the number of bytes that can be written to the
transmit FIFO
Selects which channels will be mapped to the receive
HDLC controller
Selects which bits in a channel will be used or which Sa bits
will be used by the receive HDLC controller
Selects which channels will be mapped to the transmit
HDLC controller
Selects which bits in a channel will be used or which Sa bits
will be used by the transmit HDLC controller
Access to 128-byte receive FIFO
Access to 128-byte transmit FIFO
DS21455/DS21458 Quad T1/E1/J1 Transceivers
FUNCTION