CYIL1SE3000AA-GZDC Cypress Semiconductor Corp, CYIL1SE3000AA-GZDC Datasheet - Page 40

• Manufacturer Part Number: CYIL1SE3000AA-GZDC
• Description: IC IMAGE SENSOR 3MP 369-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIL1SE3000AA-GZDC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FOT Starts Before Readout
When the EXPOSURE_1 signal goes low before the window readout has finished, the readout is interrupted after the completion of
the current line’s readout (line x in
Dual Slope Integration Timing
If the dual slope enable bit is set high, dual slope integration is
controlled through the EXPOSURE_2 pin. If the dual slope
enable bit is set low, the dual slope integration is disabled.
Figure 26
the EXPOSURE_1 pin. When pix_reset goes low, the dual slope
reset of the pixel array is activated. Bringing the EXPOSURE_2
pin high starts the dual slope integration.
Readout Modes
The sensor is configured to operate in three readout modes:
training, test image readout, and normal readout. These modes
enable correct communication between the sensor and the
customer system.
Readout of Training Sequence
By setting the TRAINING_EN and BYPASS_MODE bit, all data
channels and the sync channel transmit alternating the Idle_A
and Idle_B word. Rotating the received Idle_A and Idle_B words
in the receiver allows correcting for skew between the LVDS
outputs and the receiver clock. The Idle_A and Idle_B words are
programmed by the user.
Document Number: 001-44335 Rev. *C
shows the timing. The pix_reset signal is controlled by
EXPOSURE_1
EXPOSURE_2
EXPOSURE_1
pix_reset_ds
pix_sample
pix_sample
pix_vmem
pix_reset
pix_vmem
pix_reset
DATA
DATA
Figure
FOT
FOT
FOT
25).
Figure 26. Dual Slope Integration Timing
Figure 25. High Level Readout Timing
PRELIMINARY
L1
L1
wait till ROT
L2
L2
L3
wait till ROT
L3
wait till ROT
The start of the FOT is controlled by the falling edge of the
EXPOSURE_1 pin. The EXPOSURE_2 pin must be brought low
during FOT to be ready for the next cycle.
Setup and Hold Requirements
EXPOSURE_1 and EXPOSURE_2 are deglitched using two
chained flipflops that clock on the sensor clock. As a result, there
is no setup requirement for both signals relative to LVDS_CLKIN.
The hold requirement is 15 clock periods of LVDS_CLKIN.
Readout of Test Image
By setting the BYPASS_MODE bit high and the TRAINING_EN
bit low, the sensor is configured to output a programmable test
pattern.
The sync channel operates as in normal readout and enables
frame and line synchronization. Every data channel transmits a
fixed, programmable word to replace normal data words coming
from the ADC. In this mode, the sensor behaves as in normal
readout. The sync channel transmits programmable keywords to
allow frame and line synchronization. When not transmitting data
from the ADC, the data channels transmit the toggling Idle_A and
Idle_B words. As a result, the data stream from the sensor has
a fixed format.
L4
integration time
L x-1
integration time
L x
DS integration time
L x
wait till ROT
FOT
CYIL1SN3000AA
L1
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