CYIL1SE3000AA-GZDC Cypress Semiconductor Corp, CYIL1SE3000AA-GZDC Datasheet
CYIL1SE3000AA-GZDC
Specifications of CYIL1SE3000AA-GZDC
Related parts for CYIL1SE3000AA-GZDC
CYIL1SE3000AA-GZDC Summary of contents
Page 1
... Medical imaging ■ Industrial imaging Ordering Information Marketing Part Number CYIL1SN3000AA-GZDC Mono micro lens with glass CYIL1SE3000AA-GZDC Color micro lens with glass CYIL1SN3000-EVAL Mono micro lens demo kit Cypress Semiconductor Corporation Document Number: 001-44335 Rev. *C PRELIMINARY LUPA 3000: 3 MegaPixel High Speed ...
Page 2
Contents Features .................................................................................1 Applications ..........................................................................1 Description ............................................................................1 Ordering Information ...........................................................1 Contents ................................................................................2 Specifications .......................................................................3 Key Specifications ...........................................................3 Absolute Maximum Ratings .............................................3 Electrical Specifications ...................................................4 Overview ................................................................................6 Sensor Architecture .............................................................7 Image Sensor Core .........................................................7 Analog Front End ...........................................................9 Data Block ......................................................................12 ...
Page 3
Specifications Key Specifications Table 1. General Specifications Parameter Specifications Active pixels 1696 (H) x 1710 (V) Pixel size 8 µ µm Pixel type 6T pixel architecture Data rate 412 Mbps (32 serial LVDS outputs) Shutter type Global Pipelined ...
Page 4
Electrical Specifications Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. [ Table 4. Power Supply Ratings Boldface limits apply for MIN MAX Symbol Power Supply ...
Page 5
Table 5. Power Dissipation Power supply specifications according to Parameter Symbol Average power dissipation Power Table 6. AC Electrical Characteristics The following specifications apply for VDD = 2.5 V Parameter Symbol Input clock frequency F CLK Frame rate fps ...
Page 6
Overview The datasheet describes the interfaces of the LUPA 3000. The CMOS image sensor features synchronous shutter with a maximum frame rate of 485 fps at full resolution. The sensor contains 64 on-chip 8-bit ADCs operating at 25.75 Msamples/s each, ...
Page 7
Figure 3. Mono and Color µLens BehavioreColor Filter Array The color version of LUPA 3000 is available in Bayer (RGB) patterned color filter array. The orientation of RGB and active pixel array [0,0] is shown in Figure 4. Sensor Architecture ...
Page 8
Document Number: 001-44335 Rev. *C PRELIMINARY Figure 5. Sensor Floor Plan On chip drivers Pixel kernels Pixel array 1696 * 1710 Pixel (0,0) Column amplifiers Odd kernels 32 Even kernels X-shift register 64 ADC’ ...
Page 9
Pixel Architecture The pixel architecture shown in Figure 7 shutter combined with a high sensitivity and good Parasitic Light Sensitivity (PLS). This pixel architecture is designed µ µm pixel pitch and designed with a ...
Page 10
Programmable Dark Level A SPI controlled DAC provides the programmable gain amplifiers with a dark level. This analog voltage corresponds with the all zero output of the ADC. This dark level is tuned to optimally use the ADC range. The ...
Page 11
Table 10. AFE and ADC Parameters Parameter Input range 1.5 V–0.3 V (Single to Diff Converter; S2D) (SE to Unipolar Differential) Vblack 1.2 V–1.5 V (typical) Analog PGA gain and settings 1x–4x (6 gain settings) Input range (ADC) 0.75 ...
Page 12
Data Block The data block is positioned in between the analog front end (output stage+ADCs) and the LVDS interface. It muxes the outputs of two ADCs to one LVDS block and performs some minor data handling: ■ CRC calculation and ...
Page 13
Figure 11. LVDS Driver Programmable Drive Current Settings REG 72 <3:0> 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 LVDS Sync Channel LUPA 3000 includes a LVDS output channel to encode sensor ...
Page 14
LVDS Specifications The LUPA 3000 features a 33 channel LVDS data interface, which enables high data rates at a limited pin count with low power and noise. The LUPA 3000 guarantees 412 Mbps trans- The LUPA 3000 accepts an LVDS ...
Page 15
Table 11. LVDS Driver Specifications Parameter [ Differential logic voltage T |V (1)|–|V (0)| Delta differential voltage Common mode offset OS d|V | Difference in common mode voltage for logic 1 and ...
Page 16
On-Chip BandGap Reference and Current Biasing For current biasing and voltage reference requirements for the AFEs, ADCs, and LVDS I/O, LUPA 3000 includes a bandgap voltage reference that is typically 1.25V. This reference is used to generate the differential Vrefp–Vrefm ...
Page 17
Sequencer and Logic The sequencer generates the internal timing of the image core based on the SPI settings uploaded by the user. The user controls the following settings: ■ Window resolution ■ FOT and ROT ■ Enabling or disabling reduced ...
Page 18
Table 14. Detailed Description of SPI Registers (continued) Address Bits 32 <7:0> SOF 33 <7:0> SOL 34 <7:0> EOL 35 <7:0> IDLE_A 36 <7:0> IDLE_B 64 <6:0> Voltage Reference Adjust <2:0> bg_trim <3> <6:4> vref_trim 65 <7:0> Clock edge delay ...
Page 19
Table 14. Detailed Description of SPI Registers (continued) Address Bits 102 <7:0> Testpattern 6 103 <7:0> Testpattern 7 104 <7:0> Testpattern 8 105 <7:0> Testpattern 9 106 <7:0> Testpattern 10 107 <7:0> Testpattern 11 108 <7:0> Testpattern 12 109 <7:0> ...
Page 20
Ds_en, bit<3>. Bit to enable dual slope operation. Enabling ■ this mode allows to enlarge optical dynamic range. Sel_pre_width, bit<5:4>. Setting these 2 bits allows changing ■ the width of the sel_pre pulse that is used to precharge all Table ...
Page 21
Precharge_timer (b0000010 / d2) The precharge_timer register controls the length of the pixel precharge pulse as described in the section page 41 The pixel precharge length is expressed in the number of sensor clock periods by the following formula: Pixel ...
Page 22
Nb_of_kernels (b0000110 / d6) This register controls the window size in X. The value of the register determines the number of pixel kernels that is readout every line. The maximum number of kernels to readout is 53. The minimum number ...
Page 23
Training (b0001100 / d12) This register allows switching between different readout modes. Bits <7:2> are ignored. Training_en, bit<0>. In bypass mode, this bit is evaluated and determines if the training pattern or test image is transmitted. ■ Bypass_mode, bit<1>. This ...
Page 24
Biasing_1 (b0001111 / d15) Bias_col_amp, bits<3:0>. This register controls the biasing current of the first column amplifier. The register value must not be ■ changed. Bias_col_outputamp, bits<7:4>. This register controls the biasing current of the output column amplifier. The register ...
Page 25
Biasing_3 (b0010001 / d17) Bias_decoder_y, bits<3:0>. This register controls the biasing current of the y decoder. The register value must not be changed. ■ Bias_decoder_x, bits<7:4>. This register controls the biasing current of the last stage of the analog amplifier. ...
Page 26
EOL (b0100010 / d34) This register contains the End Of Line (EOL) keyword. Table 35. EOL Register On startup Idle_A (b0100011 / d35) This register contains the idle A keyword. Table 36. Idle_A Register On startup Idle_B (b0100100 / d36) ...
Page 27
Sensor Clock Edge Adjust Register (b1000001 / d65) The sensor clock edge adjust register allows programmable delay between the column readout and the ADC capture clock edges. The relationship is programmed to align to ±7 edges of the input high ...
Page 28
These bits allow adjusting the rising edge of the sensor clock (CLK_SEN, clk/4) position, with respect to the high speed input clock (clk) and the falling edge of the ADC sample clock (ADC_CLK, clk/8). Table 39. dly_sen ...
Page 29
ADC and LVDS Channel Powerdown Registers (b1000010- 1000110 / d66-70) Each of the 32 data channels, sync, and clock out LVDS channels are individually powered down by setting the appropriate bits of these registers. Powering down a channel stops the ...
Page 30
Table 42. Misc1 SuperBlk Control Register (continued) Value test_en, bit<4> 0 Normal operation 1 Test Mode On startup 0 atst_en, bit<5> 0 Normal operation 1 ADC analog test mode On startup 0 sblk_spare1, bit<6> 0 Normal operation 1 On startup ...
Page 31
Misc2 SuperBlk Control Register (b1001010 / d74) The misc2 superblk control register contains additional analog bias and reference controls. The bits are defined in this section. ■ bg_disable, bit <0>: This bit is provided if the on-chip bandgap needs to ...
Page 32
Testpattern 0-31 registers (b1100000- 1111111 / d96-127) A register is provided for each of the 32 data channels for LVDS data recovery calibration, alignment, and testing. A unique test pattern is programmed for each data channel and routed to the ...
Page 33
Serial Peripheral Interface (SPI ) The SPI registers have an address space of 7 bits, a<6>–a<0>, and 8 data bits, d<7>–d<0>. A single instruction bit chooses between a read or write instruction. The SPI is used only after the clock ...
Page 34
Image Sensor Timing and Readout Pixel Timing After every exposure cycle, the value on the pixel diode is trans- ferred to the pixel storage capacitor. This is controlled by Vmem, precharge, and sample signals. The duration of this operation is ...
Page 35
Frame Period = FOT + Reset length + Integration time = t1+t2+t3 To receive the frames without any overlap, the summation of reset time and integration time should always be greater than the readout time. (Reset time + Integration time) ...
Page 36
Global Shutter Mode In a global shutter, light integration occurs on all pixels in parallel, although subsequent readout is sequential. integration and readout sequence for the global shutter. All pixels are light sensitive at the same period of time. The ...
Page 37
The integration time is controlled by the external Exposure 1 pin. The relationship between the input pin and the integration time is shown in Figure 19. When the input pin Exposure 1 is asserted, the pixel array goes out of ...
Page 38
Image Format and Readout Protocol The active area read out by the sequencer in full frame mode is shown in Figure 22 shows the behavior of the data and sync channels. Document Number: 001-44335 Rev. *C PRELIMINARY Figure 21. Pixels ...
Page 39
Timing and Readout of the Sensor High Level Timing The LUPA 3000 sensor is a pipelined synchronous shutter. This indicates that light integration and readout occur in parallel, achieving the high frame rate and data throughput. The maximum frame rate ...
Page 40
FOT Starts Before Readout When the EXPOSURE_1 signal goes low before the window readout has finished, the readout is interrupted after the completion of the current line’s readout (line x in Figure FOT pix_vmem DATA EXPOSURE_1 pix_reset pix_sample Dual Slope ...
Page 41
Data Stream Figure 27 represents the data stream of the data and control channels. Data channel “i” outputs the data from column “i” of every kernel. All control words in Table 48 through the SPI. A SOF word is followed ...
Page 42
Reduced ROT Readout Mode After selecting a pixel row, the pixels need to charge a large capacitive load. This load is caused by the long metal line connecting all the pixels of a column and by the number of pixels ...
Page 43
If RESET_N_SEQ is only low for a short period of time (100 ns), the pixel array is not completely reset. Information from the previous integration cycle is still present on the photodiode. stable supply voltages stable supply voltages RESET_N RESET_N_SEQ ...
Page 44
Document Number: 001-44335 Rev. *C PRELIMINARY Figure 33. Sequence of Data from LUPA 3000 CYIL1SN3000AA Page [+] Feedback ...
Page 45
Additional Features Windowing A fully configurable window can be selected for readout. The parameters to configure this window are: X_START the start position for the X readout. Readout starts only at odd kernel positions result possible ...
Page 46
Figure 35. Dynamic Range Extended by Multiple Slope Capability In slave mode, you have full control through the pins Exposure 1 and Exposure 2. You must configure the multiple slope parameters for the application and interpret the pixel data accordingly. ...
Page 47
Figure 37. Normal Image without FPN and PRNU Correction. The fpn lines can be seen clearly in the darker and bright regions of the image. Software FPN Correction The procedure is as follows: 1. Adjust the black level with the ...
Page 48
The fpn lines in the darker regions are no longer present. However at an angle, fpn lines can be seen in the brighter region as marked in the image. These lines in the brighter regions can be eliminated by applying ...
Page 49
Figure 39. Image after FPN and PRNU Correction Note Dark and bright images needs to be updated whenever gain settings, ROT, FOT and temperature of the sensor are changed. Document Number: 001-44335 Rev. *C PRELIMINARY CYIL1SN3000AA Page ...
Page 50
Package Information Pin Definitions The package has 369 pins. Table 50 lists 228 pins. The remaining pins are used as die attach ground pins. Table 50. Pin List Finger Number Pin Number ...
Page 51
Table 50. Pin List Finger Number Pin Number ...
Page 52
Table 50. Pin List Finger Number Pin Number ...
Page 53
Table 50. Pin List Finger Number Pin Number 126 W15 127 V15 128 U15 129 T15 130 T16 131 U16 132 V16 133 W16 134 W17 135 V17 136 U17 137 T17 138 T18 139 U18 140 V18 141 W18 ...
Page 54
Table 50. Pin List Finger Number Pin Number 169 C20 170 C21 171 B21 172 A21 173 B20 174 A20 175 A19 176 B19 177 B18 178 A18 179 B17 180 A17 181 A16 182 B16 183 B15 184 A15 ...
Page 55
Table 50. Pin List Finger Number Pin Number 212 D7 213 C7 214 B7 215 C6 216 B6 217 D6 218 D5 219 C5 220 B5 221 A6 222 A5 223 B4 224 A4 225 F6 226 R6 227 T19 ...
Page 56
224 222 221 210 209 223 220 216 214 208 219 215 213 207 ...
Page 57
Mechanical Specifications Table 51. Mechanical Specifications Mechanical Specifications Die thickness Die center, X offset to the center of package Die center, Y offset to the center of the package Die position, X tilt Die position, Y tilt Die placement accuracy ...
Page 58
Package Diagram Figure 41. LUPA 3000 µPGA Package Diagram (Top View) INDEX MARK (PLATING OPTION) 4X (0.50X45°) CHAMFER Document Number: 001-44335 Rev. *C PRELIMINARY +0.29 GLASS PIN Fe-Ni-Co ALLOY CYIL1SN3000AA 4X (R 0.20) 0.15 001-54817 *A 369X Page 58 of ...
Page 59
Figure 42. LUPA 3000 µPGA Package Diagram (Bottom View) 369X 4X (0.25X45°) CHAMFER Document Number: 001-44335 Rev. *C PRELIMINARY (AT PIN BASE) (AT PIN BASE 369X Ø0.97 CYIL1SN3000AA ALUMINA ...
Page 60
Glass Lid The LUPA 3000 image sensor uses a glass lid without any coatings. Figure 43 shows the transmission characteristics of the glass lid. Figure 43. Transmission Characteristics of the Glass lid Handling Precautions For proper handling and storage conditions, ...
Page 61
... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...