CYIL1SE3000AA-GZDC Cypress Semiconductor Corp, CYIL1SE3000AA-GZDC Datasheet - Page 35

• Manufacturer Part Number: CYIL1SE3000AA-GZDC
• Description: IC IMAGE SENSOR 3MP 369-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIL1SE3000AA-GZDC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Frame Period = FOT + Reset length + Integration time
To receive the frames without any overlap, the summation of
reset time and integration time should always be greater than the
readout time.
(Reset time + Integration time) > Readout time
Note For more information, refer the Cypress application note
AN57864.
In global shutter mode, the whole pixel array is integrated simul-
taneously.
Windowing
Windowing is easily achieved by SPI. The starting point of the x
and y address and the window size can be uploaded. The
minimum step size is in the x direction is 32 pixels (choose only
Operation and Signaling
Digital Signals
LUPA 3000 operates in slave mode; the pixel array of the image sensor requires different digital control signals. The function of each
signal is listed in
Table 47. Overview of Digital Signals
Document Number: 001-44335 Rev. *C
Signal Name
Exposure_2
Exposure_1
SPI_MOSI
SPI_MISO
RESET_N
SPI_CLK
SPI_CS
ROT
FOT
CLK
= t1+t2+t3
Table
47..
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
I/O
PRELIMINARY
Figure 17. Timing Diagram
Output pin for FOT
Output pin for ROT
Integration pin dual slope
Integration pin first slope
Sequencer reset, active LOW
System clock (206 MHz)
SPI chip select
SPI clock
Data line of the SPI, serial input
Data line of the SPI, serial output
multiples of 32 as a start or stop addresses). The minimum step
in the y direction is 1 line (every line can be addressed in the
normal mode).
Table 46. Typical Frame Rates at 206 MHz
Image Resolution
1600 x 1200
1280 x 1024
1696 x1710
640 x 480
512 x 512
256 x 256
128 x 128
(X*Y)
Comments
Frame Rate
10704
26178
1001
2653
3808
(fps)
484
712
CYIL1SN3000AA
Frame Period(ms)
2.065
1.404
1.000
0.377
0.263
0.093
0.038
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