CYIL1SE3000AA-GZDC Cypress Semiconductor Corp, CYIL1SE3000AA-GZDC Datasheet - Page 20

• Manufacturer Part Number: CYIL1SE3000AA-GZDC
• Description: IC IMAGE SENSOR 3MP 369-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIL1SE3000AA-GZDC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Table 15. Sequencer Register
ROT_timer (b0000001 / d1)
The ROT_timer register controls the length of the ROT. The ROT length, in number of sensor clock periods, is expressed by the
formula: ROT length = ROT_timer + 2
The relation between the Row Overhead Time and the ROT pin is described in the section
Table 16. ROT Timer Register
Document Number: 001-44335 Rev. *C
Powerdown, bit <0>
Reset_n_seq, bit<1>
Red_ROT, bit<2>
0
1
On startup
Ds_en, bit<3>
Sel_pre_width, bit<5:4>
Ds_en, bit<3>. Bit to enable dual slope operation. Enabling
this mode allows to enlarge optical dynamic range.
Sel_pre_width, bit<5:4>. Setting these 2 bits allows changing
the width of the sel_pre pulse that is used to precharge all
Value bit<4:0>
On startup
On startup
On startup
On startup
On startup
00000
xxxxx
Value
00
01
10
11
0
1
0
1
0
1
ROT length is 35 sensor clocks, 140 master clocks.
ROT length is <N+2> sensor clocks (<N+2>*4 master clocks) where N is the
register value
00111 (9 sensor clocks)
Normal operation
Image core in power down
0
Sequencer kept in reset
Normal operation
1
Long ROT mode
Reduced ROT mode
1
Disable dual slope operation
Enable dual slope operation
0
Sel_pre is 1 sensor clock period long (4 master clocks)
Sel_pre is 2 sensor clock periods long (8 master clocks)
Sel_pre is 3 sensor clock periods long (12 master clocks)
Same effect as ‘10’ setting
00
PRELIMINARY
Effect
Effect
.
column lines at the start of every ROT. Changing these bits
does not change the total ROT length.
ROT Pin
on page 42 Bits <7:5> are ignored.
CYIL1SN3000AA
Page 20 of 61
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