CYIL1SE3000AA-GZDC Cypress Semiconductor Corp, CYIL1SE3000AA-GZDC Datasheet - Page 34

• Manufacturer Part Number: CYIL1SE3000AA-GZDC
• Description: IC IMAGE SENSOR 3MP 369-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIL1SE3000AA-GZDC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Image Sensor Timing and Readout
Pixel Timing
After every exposure cycle, the value on the pixel diode is trans-
ferred to the pixel storage capacitor. This is controlled by Vmem,
precharge, and sample signals. The duration of this operation is
the Frame Overhead Time (FOT). At the beginning of the FOT,
Vmem is brought low, and precharge and sample are brought
high. The precharge pulse ensures that the old information on
Considerations in Pixel Timing
The length of the FOT_TIMER, PRECHARGE_TIMER, and
SAMPLE_TIMER influences the final image quality.
■
■
■
The length of pixel_reset influences image lag. The pixel must
be reset for at least 3 µs.
Frame Rate and Windowing
Frame Rate
The frame rate depends on the input clock, the frame overhead
time (FOT), and the row overhead time (ROT). The frame period
is calculated as follows:
1 kernel = 32 Pixels
1 Gran. Clock = 4 clock periods
Table 45. Clarification of Frame Rate Parameters
Document Number: 001-44335 Rev. *C
FOT
Parameter
Precharge pulse: The pixel precharge prevents image lag. A
very short pulse results in image lag.
Sample pulse: A shorter sample results in a reduced dark level.
FOT_TIMER register: The vmem signal must charge all pixel
storage capacitors simultaneously. This is a large combined
capacitance (96 nF) and Vmem takes some time to stabilize.
Readout must start only after Vmem is stable.
Frame Overhead
Time
Comment
The FOT does a frame transfer
from pixel diode to the pixel
storage node. During this
transfer period, the sensor is not
readout. The FOT length is
programmable. The default
length is 3.2 µs.
Clarification
PRELIMINARY
Figure 16. Pixel Timing
the storage node is destroyed. This ensures there is no image
lag. After the falling edge of the precharge pulse, the sampling
operation on the storage node is completed during the high level
of sample.
After the falling edge of sample, Vmem is brought high. The rise
in Vmem compensates for the voltage loss in the last source
follower in the pixel. The readout begins after this. The pulse
length is controlled by the user. The registers that control this are
listed in the following section.
Table 45. Clarification of Frame Rate Parameters
Frame period = FOT + Nr. Lines * (ROT + Nr. Pixels/4 * Data
Period)
Or
Frame period = FOT + Nr. Lines * (ROT + Nr. kernels * Granu-
larity Clock cycles)
Example
Readout time for full resolution at nominal speed of 206 MHz
(4.854 ns) is given by
Frame Period = 3.2 µs + (1710 * (176 ns + 1696/4*2.427ns)) =
2.063 ms
Or
Frame Period = 3.2 µs + (1710 * (176 ns + 53*19.4174ns)) =
2.063 ms
Frame Rate =485 FPS
Alternatively, frame rate can also be expressed in terms of reset
length and Integration time rather than readout time.
The sequence of events shown in
integration and readout in pipelined global shutter mode.
ROT
Nr. Lines
Nr. Pixels
Data Period 0.5 x Clock
Parameter
Row Overhead
Time
Number of lines
readout each
frame
Number of pixels
readout each line
period = 2.427 ns
Comment
The ROT transfers the pixel
output to the column amplifiers.
Default ROT is 176 ns.
Default is 1710 lines.
Default is 1696 pixels.
Because the outputs operate at
DDR, the data period is half the
clock period (206 MHz clk).
CYIL1SN3000AA
Figure 17
Clarification
occurs during
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