CYIL1SE3000AA-GZDC Cypress Semiconductor Corp, CYIL1SE3000AA-GZDC Datasheet - Page 11

• Manufacturer Part Number: CYIL1SE3000AA-GZDC
• Description: IC IMAGE SENSOR 3MP 369-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIL1SE3000AA-GZDC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

.
Table 10. AFE and ADC Parameters
Each pair of odd and even kernel AFE + ADC channels are
individually powered down with its associated LVDS serialization
channel. This is controlled through bits in SPI registers 66–70
(decimal). Logic 1 is the power down state. The POR defaults are
logic 0 for all channels powered on.
Protocol Layer
Digital data from the ADCs is reorganized in the protocol layer
before it is transferred to the LVDS drivers. The following
operations are performed in the protocol layer:
■
■
■
■
Document Number: 001-44335 Rev. *C
Input range
(Single to Diff Converter; S2D)
Vblack
Analog PGA gain and settings
Input range (ADC)
ADC type
ADC resolution
Sampling rate per ADC
ENOB
DNL
INL
Power supply
Total AFE + ADC latency
Total AFE + ADC power
(32 channels = 64 AFE + ADC)
Multiplexing of two ADCs to one output data channel
Addition of the CRC checksum to the data stream. This
operation is done row by row. A new CRC checksum is
calculated for every new row that is readout.
Switching readout mode. The LUPA 3000 sensor is
programmed to operate in two other readout modes: training
and test image modes. These modes synchronize the readout
circuitry of the end user with the sensor.
Assembling the data stream of the synchronization channel.
(msb first)
Parameter
datain
lsb
x0
Figure 9. Equivalent Polynomial Representation in Serial Format
1.5 V–0.3 V
(SE to Unipolar Differential)
1.2 V–1.5 V (typical)
1x–4x
(6 gain settings)
0.75 V–1.75 V
Pipelined (four ADC clock latency)
8 bits
26.5 MSPS
7.5 bits
±0.5 LSB
±1.0 LSB
2.5 V ±0.25V
44 Master clocks
400 mW (at 2.5 V)
x1
Parameter Value (typical)
PRELIMINARY
x2
x
8
+ x
x3
6
+ x
CRC
LUPA 3000 implements a Cyclic Redundancy Check (CRC) for
each row (line) of processed data to detect errors during the high
speed transmission. CRC provides error detection capability at
low cost and overhead.
The CRC polynomial implemented for LUPA 3000 is:
x^8+x^6+x^3+x^2+1.
The CRC result is transmitted with the original data. When the
data is received (or recovered), the CRC algorithm is reapplied
and the latest result compared to the original result. If a
transmission error occurs, a different CRC result may be
obtained. The system then chooses to operate on the detected
error or has the frame resent.
The CRC shift register is initialized with logic 1s at reset to
improve bit error detection efficiency.
Referring to
and inserted into the serial data stream. Bit 0 of SPI register 71
(decimal) is an enable bit to insert the CRC checksum. CRC is
enabled when a logic 1 is written to this bit. This is the default
(POR) value. Bit 1 of this register allows calculation and insertion
of a CRC checksum to the “synchronization” channel. No
checksum is attached by default.
3
+ x
x4
2
S2D performs inversion. Referenced from Vblack
Dark or black level reference from SPI
programmable DAC. 0.01 µF to gnd.
3-bit SPI programmable. 1x, 1.5x, 2x, 2.25x, 3x, 4x
1V maximum Vrefp-Vrefm (2 Vp-p maximum)
With digital error correction (no missing codes)
Maximum 30 MSPS
Effective number of bits
No missing codes
5.5 ADC clocks = 1/8 of master clk
160 mA
+ 1
Figure
9, the CRC value is calculated for each row
x5
Comment
x6
CYIL1SN3000AA
msb
x7
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