LM98513CCMTX/NOPB National Semiconductor, LM98513CCMTX/NOPB Datasheet - Page 22

• Manufacturer Part Number: LM98513CCMTX/NOPB
• Description: IC DIGITAL COPIER 10BIT 56TSSOP
• Manufacturer: National Semiconductor

Specifications of LM98513CCMTX/NOPB

• Number Of Bits: 10
• Number Of Channels: 2
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Compliant

The LM98513 Clock
Although the LM98513 is tested and its performance guaranteed
with a 25MHz clock, it typically will function with clock
frequencies ranging from 1MHz to 30MHz. Performance is best
if the clock rise and fall times are less than 3ns and the clock
trace is terminated near the clock input pin with a series RC
network consisting of a 100Ω resistor and a 47pF capacitor.
Layout and Grounding Techniques
The proper routing of all signals and relevant grounding
techniques are essential to ensure the best signal-to-noise ratio
and dynamic performance possible. Separate analog and digital
ground planes ease meeting the datasheet limits. The analog
ground plane should be low impedance and free from noise of
other components of the system. All bypass capacitors should
be located as close to the pin as possible and connected to the
appropriate ground plane with short traces (<1cm). The analog
input should be isolated from noisy signal traces to avoid
coupling of spurious signals into the input.
Figure 20 provides an example of a suitable layout, including
power supply routing, ground place separation, and bypass
capacitor placement. All input amplifiers, filters, and reference
components should be placed on or over the analog ground
plane. All digital circuitry and I/O lines should be placed over
and grounded via to the digital ground plane. Digital and analog
signal lines should never run parallel to each other in close
proximity with each other. These signals should only cross when
absolutely necessary and then only at 90° angles.
Dynamic Performance
The LM98513 is AC tested and its dynamic performance is
guaranteed. The clock source driving the MCLK input must be
free of jitter. For best AC performance, the clock source should
be isolated from other system digital circuitry with a clock tree
buffer(s). Meeting noise specifications depends largely upon
keeping digital noise out of the analog input of the LM98513.
Common Application Pitfalls
Driving the inputs (analog or digital) beyond the power supply
potential. For proper operation, all input potentials should not be
greater than 300mV above that of the power supply. It is not
©
2005 National Semiconductor Corporation
APPLICATIONS INFORMATION (Continued)
510 Ω
0.1µF
0.1µF
VREFP
VREFN
Figure 20: ADC, DAC Reference Bypassing and internal ADC Ladder Buffer
AV+
Ladder
Buffer
Switches closed: Buffer Enable=1
Switches open: Buffer Enable=0
22
uncommon for high speed digital circuits (e.g. 74F and 74AC
devices) to exhibit undershoot that falls to a potential greater
than 1.0 Volt below the ground potential and overshoot that rises
to a potential greater than 1.0 Volt above the power supply
potential. A series resistor of 50Ω to 100Ω in the digital signal
will, in most cases, eliminate this problem.
Attempting to drive a high capacitance digital data bus. The
more capacitance the output drivers have to charge for each
conversion output, the more instantaneous digital current is
required from the DV+ I/O and DGND I/O supply pins. These
large charging current spikes can couple into the analog section
and subsequently may degrade dynamic performance of the
system. Adequate bypassing and maintaining separate analog
and digital ground planes will reduce this problem on the
application system board. Buffering the digital data outputs may
be necessary if the data bus being driven by the LM98513 is
heavily loaded. Dynamic performance may also be improved by
adding series resistors of 47Ω at each digital output.
Driving the reference pins with devices that cannot source
or sink the current required by the reference resistor ladder.
As mentioned previously, any devices driving the reference
resistor ladder must source sufficient current into the top of the
ladder. Additionally, the device connected to the bottom of the
ladder must be able to sink the necessary amount of current to
keep the reference voltage(s) stable. If the reference resistor
ladder voltages are not stable the converter output will not
generate predictable output codes.
AV+
VREFT
VREFB
10µF
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0.1µF
0.1µF