LM98513CCMTX/NOPB National Semiconductor, LM98513CCMTX/NOPB Datasheet - Page 19

• Manufacturer Part Number: LM98513CCMTX/NOPB
• Description: IC DIGITAL COPIER 10BIT 56TSSOP
• Manufacturer: National Semiconductor

Specifications of LM98513CCMTX/NOPB

• Number Of Bits: 10
• Number Of Channels: 2
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Compliant

Serial Interface Read/Write Description
Writing to the serial registers
To write to the serial registers, the timing diagram shown in
Figure 15 must be met. First SEN is toggled low. SI DATA may
then be clocked in, and the data present on the rising edge of
the serial clock is loaded in. The data continues to be clocked
in, until SEN toggles high. The data present in the register is the
last 15 bits of data sent before SEN toggled high. Therefore, for
example, if 20 bits were sent when SEN was toggled low, the
first 5 bits were discarded, and the data loaded are the
remaining 15 bits. As seen in figure 15, these 15 bits are
composed of 8 data bits, 4 address bits, 2 CE bits, and 1 read/
write bit. When writing to the registers, the read/write bit must
be low. When SEN toggles high, the register is written to, and
the LM98513 now functions with this new data.
Power-On and Reset Timing Specifications
The following specifications apply for AV+ = DV+ = DV+ I/O = 3.3V, C
limits apply for TA = T
Power-On and Reset Timing Details
©
2005 National Semiconductor Corporation
Symbol
t
t
t
PORS
PORH
POR
Power-On or Reset Data Setup
Power-On or Reset Data Hold
Power-On or Reset Time
MIN
to T
Parameter
Power-On
CE1-CE0
Time
Time
Reset
MAX
or
: all other limits T
Figure 16: Power-On or Reset Timing
XXX
A
Device settling time
settling where data
settling where data
Setup time during
power-on or reset
power-on or reset
after power-on or
= 25
Hold time after
must be valid
must be valid
Conditions
reset pulse
o
C
19
t
POR
Reading the serial registers
To read the serial registers, the timing diagram shown in Figure
14 must be met.When SEN is toggled low, and data is loaded as
described above in the writing sequence. When SEN toggles
high, the new 15 bit word is considered, except this time the
read/write bit should be a 1 indicating a read. The 8 data bits
are not considered, but act only as place holders. When SEN
toggles low again, the data that resides at the address
considered in the previous read or write routine, begins clocking
out SO DATA. The data streams out MSB-LSB as shown in
Figure 14. Whether a read or a write was invoked in the
previous sequence, the SO DATA will clock out the contents of
the address considered in the previous sequence.
L
= 10pF, and f
t
PORS
VALID
note 9
Min
5
MCLK
t
= 25MHz unless otherwise noted. Boldface
PORH
Typical
note 8
note 9
Max
270
0
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Units
ns
ns
ns