LM98513CCMTX/NOPB National Semiconductor, LM98513CCMTX/NOPB Datasheet - Page 13

• Manufacturer Part Number: LM98513CCMTX/NOPB
• Description: IC DIGITAL COPIER 10BIT 56TSSOP
• Manufacturer: National Semiconductor

Specifications of LM98513CCMTX/NOPB

• Number Of Bits: 10
• Number Of Channels: 2
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Compliant

System Overview
Black Level Correction
CCD signal processors require a reference level for the proper
handling of input signals; this reference level is commonly
referred to as the black level. The LM98513 is designed to
determine a signal’s black level during the CCD imager’s optical
black pixels.The LM98513 provides both an analog clamp and a
digital black level correction loop as shown in Figure 9. The
timing for these pulses is shown in Figure 6.
Black Level Clamp
Black level correction may be performed through one of two
available methods: automatic or manual. In automatic mode, the
black level is determined from the ADC output during black
pixels by asserting the BLKCLP input of the LM98513 as shown
in Figure 6. The ADC black level output value is then averaged
over a programmed number of pixels and subtracted from the
desired black level code stored in the output black level register.
The result of the subtraction may then be integrated by a preset
scaling factor, effectively smoothing any sharp transitions
present in the black level signal, before the resulting calculated
offset is finally applied to the input of the PGA as an offset level
©
Black Pixels
2005 National Semiconductor Corporation
200−510 Ω
Figure 9: Digital Black Level Correction Loop
S/H
Offset Level Register
0.1µF
0.1µF
+
DAC
PGA
(Continued)
VREFP
VREFN
Integration
Offset
ADC
Black Level Register
AV+
Averaging
Figure 10: The ADC Ladder Buffer.
Pixel
-
10
Calibration
Automatic
Output
BLKCLP
Data
Offset
Ladder
Buffer
13
Switches closed: Buffer Enable=1
Switches open: Buffer Enable=0
generated by the DAC. The offset integration scaling factor is
stored in two bits of the black level clamp control register, and
the values available range from full offset to offset divided-by-16.
Use of the automatic mode involves enabling the black level
offset auto-calibration bit in the black level clamp control register
through the serial interface.The manual method is intended for
use with processing systems where the desired black level
correction loop is external to the LM98513. In this mode the
external processor may store offset values in the offset level
registers.
The BLKCLP pulse may be generated internally automatically by
setting bit [1] of the Digital Black Level Correction Register to a
“1”. This is the default condition of the LM98513. The automatic
BLKCLP pulse begins 10 MCLK periods after the falling edge of
the CLPIN pulse and ends after the programmed number of
pixels have been averaged.
Internal Timing Generation
The CCD sampling clock may be overridden by the user via the
SHD clock input. As depicted in Figure 4 there is a signal
generated internally for input sampling referred to as SAMPLE.
This signal provides the rising edge reference for the sampling of
the CCD input signal. The timing of the SAMPLE is derived from
the clock; therefore, shifting the clock phasing with respect to the
CCD input signal would also shift the rising and falling edges of
SAMPLE. The actual sampling of the CCD’s reference level and
video signal is performed on the falling edge of the SAMPLE
signal. The user may modify the position of the falling edges
where the sampling of the CCD input occurs by driving SHD
input of the LM98513. The falling edge of SHD will override the
falling edge of SAMPLE and cause the duration of the sample
pulse to shorten accordingly. As is evident in Figure 4 the falling
edge of SHD should not occur earlier than t
edge of MCLK.
VIN Test Option
The LM98513 may be placed into test mode for system
debugging capability. When in test mode, the ODD and EVEN
channel inputs are both internally connected to the VIN TEST
input. Test mode is activated (and de-activated) via the serial
interface.
AV+
VREFT
VREFB
10µF
SHD
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after the rising
0.1µF
0.1µF