LM98513CCMTX/NOPB National Semiconductor, LM98513CCMTX/NOPB Datasheet - Page 16

• Manufacturer Part Number: LM98513CCMTX/NOPB
• Description: IC DIGITAL COPIER 10BIT 56TSSOP
• Manufacturer: National Semiconductor

Specifications of LM98513CCMTX/NOPB

• Number Of Bits: 10
• Number Of Channels: 2
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Compliant

Register Data
Analog Input Control Register
Register Name Analog Input Control
Address
Mnemonic
Type
Reset Value
Offset level Registers
Register Name Even Channel offset level
Address
Mnemonic
Type
Reset Value
Register Name Odd Channel Offset Level
Address
Mnemonic
Type
Reset Value
©
2005 National Semiconductor Corporation
[2:1]
[7:0]
[7:0]
Bit
Bit
Bit
[4]
[3]
[0]
Analog Power
SHD Polarity1
Offset Level
Offset Level
CLPIN Mode
Bit Symbol
Bit Symbol
Bit Symbol
Test Mode
Signed
Signed
Enable
Select
Select
Down
6 Hex
AIC
Read/Write
0000 0000 Binary
8 Hex
A0E
Read/Write
1000 0000 Binary
9 Hex
AOO
Read/Write
1000 0000 Binary
(continued)
Digital representation of the offset
level to be applied to the input of
the PGA. Please see Figure 11 for
details regarding the DAC input
format.
Digital representation of the offset
level to be applied to the input of
the PGA. Please see Figure 11 for
details regarding the DAC input
format.
Internally connects the VIN
TEST pin to both the EVEN and
ODD inputs.
Cuts power to the on-chip
analog circuitry including the
PGA and ADC.
00 CLPIN gated by PULSE
01 CLPIN (ungated)
10 Reserved
11CLPIN gated by SAMPLE
Selection of the polarity of the
SHD timing clock.
0
1
Active-Low
Active-High
Description
Description
Description
16
Software Control Registers
Register Name Even Channel Software Control
Address
Mnemonic
Type
Reset Value
Register Name Odd Channel Software Control
Address
Mnemonic
Type
Reset Value
[4:3]
[4:3]
Bit
Bit
[2]
[1]
[0]
[2]
[1]
[0]
ADC Ladder
Bit Symbol
Bit Symbol
Reference
Set to “0”
Set to “0”
Analog
Analog
Enable
Enable
Analog
Analog
Enable
Enable
Output
Output
Output
Output
Select
Select
Buffer
Buffer
ADC
A Hex
SCE
Read/Write
XXX0 0000 Binary
B Hex
SCO
Read/Write
XXX0 0000 Binary
Routes the selected even channel
internal analog signal to the
differential analog output pins
AOUT+ EVEN and AOUT- EVEN.
00 S/H Stage
01
10
11
Enables the differential analog
output pins AOUT+ EVEN and
AOUT- EVEN.
pins should not be connected.
Enables the ladder buffer for the
ADC ladder references (VREFT &
VREFB).
0
1
This bit must be set to “0” for
proper reference voltages.
Routes the selected odd channel
internal analog signal to the
differential analog output pins
AOUT+ ODD and AOUT- ODD.
00
01
10
11
Enables the differential analog
output pins AOUT+ ODD and
AOUT- ODD. Otherwise, the pins
should not be connected.
0
1
This bit must be set to “0” for
proper reference voltages.
buffer disabled
buffer enabled
ladder buffer enabled
ladder buffer disabled
PGA Stage 3
PGA Stage 3
PGA Stage 1
PGA Stage 2
S/H Stage
PGA Stage 1
PGA Stage 2
Description
Description
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Otherwise, the