LM98513CCMTX/NOPB National Semiconductor, LM98513CCMTX/NOPB Datasheet - Page 14

• Manufacturer Part Number: LM98513CCMTX/NOPB
• Description: IC DIGITAL COPIER 10BIT 56TSSOP
• Manufacturer: National Semiconductor

Specifications of LM98513CCMTX/NOPB

• Number Of Bits: 10
• Number Of Channels: 2
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Compliant

System Overview
ADC Ladder Buffers
The top and bottom voltages of ADC reference ladder (VREFT &
VREFB) define the analog input range. These reference
voltages may experience a small amount of droop under certain
operating conditions. For example, high operating frequencies
or abrupt changes in input. An internal buffer is available to
reduce this droop, if it occurs. The buffer is enabled by setting bit
[1] of the Even/Odd Channel Software Control registers. (See
Figure 10.)
Serial Interface and Configuration Registers
There are many options available to the user that may be
programmed via the LM98513’s serial interface. Configuration
values are stored in registers for use by several functions such
as programmable gain, offset, black level, and digital black level
correction options. See ”Register Memory Map” on page 15.
Upon power-up or external reset, the configuration registers will
contain their respective default values. The master MCLK input
is required to be running during serial interface commands.
Each command entered through the serial interface must have a
minimum of 15 bits (see Figure 14 and Figure 15). In addition,
note that after a write command, the data written will be
outputted during the next command (for verification). Likewise, a
read command requires an additional command after issuing the
read command to read back the data from the register.
Chip Enable
A chip enable function is provided for use in systems with
multiple LM98513s attached to a common serial interface bus.
The two chip enable pins (CE0 and CE1) should be driven either
high or low during power-on or reset to indicate the device
address. Subsequently, this address is included in the serial
interface address as the two most significant bits (see Figure 14
and Figure 15).
Analog Output Option
The LM98513 supports the option of driving the differential
analog output pins with analog signals normally internal to the
device. For more information, see ”Software Control Registers”
on page 16.
Analog Level Offset
The offset level registers store the offset value that is required to
meet the respective channel’s black level requirements. These
registers are read-only when automatic offset calibration is
enabled. It should be noted that each offset DAC step (1 LSB)
corresponds to a 0.5 LSB step at the ADC output. Therefore, if
an offset of 20 digital codes is desired at the ADC output, a
digital code value of 40 should be stored in the offset level
register(s). As a result, the maximum offset seen at the ADC
output as a result of digital code values stored in the offset level
register(s) is ±64 codes. It is possible to increase the digital
output range of the offset level DAC, resulting in an increased
maximum ADC output code corresponding to a given DAC
input. For more information on increasing the DAC range,
please see ”Offset Level DAC Range Adjustment” on page 21.
Output Black Level
The output black level register is an 8-bit word stored by the
user that specifies the desired ADC output level corresponding
to optical black. For example, a user who requires an ADC
output level of 16 for black pixels would write this value into the
register. Upon programming this register, assertion of the
BLKCLP signal activates the digital black clamp loop and the
black level is steered toward the value stored in the output black
level register. The digital black clamp loop is only limited in it’s
©
2005 National Semiconductor Corporation
(Continued)
14
range by the offset DAC’s range (see “offset level DAC Range
Adjustment on page 21”).
Software Control
There is a software control register available for each channel
accessible via the serial interface.
registers provide selections for internal referencing options and
analog outputs for debugging purposes. Please refer to the
register data descriptions for more information on the software
control registers.
Power Level Control
The LM98513 is equipped with two power trim registers that
may be used to adjust power levels of various circuits internal to
the device. In its default condition, the LM98513 is set for
optimum power and performance, and modifying the values
stored in the power level control registers will affect performance
as a result of the change in power level(s). In applications where
maximum performance is desired, the default values should be
used. Otherwise, power levels may be decreased at the slight
expense of performance. Please refer to the register data
descriptions for more information regarding the power level
control registers.
Offset Integration
The clamping of the ADC output during optical black pixels can
be controlled to slow down or damp changes in offset values
calculated as a result of the digital black clamp loop. Each time
the BLKCLP signal is activated the ADC output is compared to
the desired value of black (See Black Pixel Averaging). If the
output does not match the desired value during comparison, an
error or deviation value results. The user has the option of
integrating either all or a programmable fraction of this deviation
into the previously calculated offset value. This has the effect of
slowing down the offset convergence resulting in a calculation
for offset that is less susceptible to noise.
Black Pixel Averaging
In order to obtain a snapshot of the current value for black (for
comparison with the desired level of black) the ADC output is
sampled upon activation of BLKCLP. Since a single optical black
pixel is unlikely to be an accurate representation of the black
level, a number of black pixels are averaged. The number of
pixels to be averaged during optical black is another
programmable parameter of the LM98513. The ability to select
the number of pixels to be averaged provides greater flexibility
allowing the LM98513 to be used with different CCDs having
differing number of black pixels.
DAC Format
There are two available formats for the input to the offset DAC.
The format is changed via the configuration bit in the digital
black level clamp control register (Reg 0x05, bit[6])..
00000000
00000001
10000000
10000001
01111111
11111110
11111111
DAC
Figure 11: DAC Formats
Default
Format
+0.78mV
+99.2mV
-99.2mV
-0.78mV
+100mV
-100mV
+/- 0mV
The software control
Optional
Format
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+0.78mV
+100mV
-0.78mV
-99.2mV
+/- 0mV
+/- 0mV
-100mV