LM98513CCMTX/NOPB National Semiconductor, LM98513CCMTX/NOPB Datasheet
LM98513CCMTX/NOPB
Specifications of LM98513CCMTX/NOPB
Related parts for LM98513CCMTX/NOPB
LM98513CCMTX/NOPB Summary of contents
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... Facsimile Equipment Desktop Publishing Flatbed or Handheld Color Scanners High-speed Document Scanner System Block Diagram CCD/CIS Sensor Sensor Drivers 2005 National Semiconductor Corporation © Rev 3.3 March 2005 Features 3 Volt Single Power Supply Low Power CMOS Design 4 Wire Serial Interface 2.5 Volt Data Output Levels ...
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... DV+ DGND Vin Test VREFT ODD SEN AOUT- ODD AOUT+ ODD VCLP ODD VIN ODD SDO AGND AV+ AV+ SCLK SHP 2005 National Semiconductor Corporation © Black Level Offset Clamp / DAC Averaging 10-Bit A/D PGA S/H Converter Black Level Offset S/H Clamp / DAC ...
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... DV+ 42 0.1µF 10µF DGND 3V 14 DV+ 15 0.1µF DGND 10µ 0.1µF 0.1µF 0.1µF Video Inputs 2005 National Semiconductor Corporation © Commercial (0°C ≤ T ≤ +70°C) A LM98513 CCMT Copier Control Serial Control Bus LM98513 Digital Video Bus ...
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... VCLP ODD 2005 National Semiconductor Corporation © Description +3.3 Volt power supply for the analog circuits. Bypass supply each supply pin with 0.1µF and 10µF capacitors in parallel. +3.3 Volt power supply for the analog circuits. Bypass supply each supply pin with 0.1µ ...
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... DOUT8 DOUT9 O D 2005 National Semiconductor Corporation © Description Odd channel analog input signal. AC-couple to imager output through a 0.1µF capacitor. Serial interface output port. Analog ground return. Power supply for the analog circuits. Bypass supply each supply pin with 0.1µF and 10µ ...
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... Legend: (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal 10k (PD=Pull Down with an internal 10K Ω resistor.). 2005 National Semiconductor Corporation © Description Power supply for the digital output driver circuits. Bypass supply each supply pin with 0.1µF and 10µF capacitors in parallel. ...
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... The following specifications apply for AV+ = DV+ = DV+ I/O = 3.3V, C limits apply for all other limits T MIN MAX Symbol Parameter PWR Average Power Dissipation 2005 National Semiconductor Corporation © Operating Ratings (Notes 1 & 2) 4.2V Operating Temperature Range -0.3V to 4.2V All Supply Voltages -0. Voltage Range ± ...
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... T MIN MAX Symbol Parameter Resolution Offset Adjustment Range DAC Step Size Temperature Drift Offset Error Vrefp Top of Reference Ladder Vrefn Bottom of Reference Ladder 2005 National Semiconductor Corporation © = 10pF, and f = 25MHz unless otherwise noted. Boldface L MCLK Min Conditions note 9 = 10pF, and f = 25MHz unless otherwise noted ...
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... Clock Input Rise and Fall Time rc fc Pipeline Delay (Latency) t Data valid time VALID t Output Data Hold Time OH t Output Delay Time OD 2005 National Semiconductor Corporation © = 10pF, and f = 25MHz unless otherwise noted. Boldface L MCLK Min Conditions note 9 PGA Gain = 0.0dB PGA Gain = 20 ...
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... Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book, for other methods of soldering surface mount devices. Note 7: The analog inputs are protected as shown below. Input voltage magnitude up to 500mV beyond the supply rails will not damage this device ...
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... Timing shown above is for SHD polarity active-high (Bit [0] in Analog input control register = 1). Digital Output Timing n+1 n+2 EVEN n n+1 n+2 ODD MCLK 10% n-7 n-6 OUTPUT DATA 2005 National Semiconductor Corporation © t SHD Figure 4: Input Sample Timing DIS Figure 5: Digital Output Data Timing 11 n+7 n+8 n+9 n+7 n+8 n+9 t ...
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... Figure 6. Asserting CLPIN causes the input pin (Vin shorted to the voltage VCLP, as shown in Figure 7. There are three modes available to control precisely where the CLPIN pulse will clamp the CCD waveform.These 2005 National Semiconductor Corporation © Optical Black Pixels Dummy Pixels ...
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... VREFP 0.1µF VREFN 0.1µF 200−510 Ω 2005 National Semiconductor Corporation © generated by the DAC. The offset integration scaling factor is stored in two bits of the black level clamp control register, and Black Level Register the values available range from full offset to offset divided-by-16. ...
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... BLKCLP signal activates the digital black clamp loop and the black level is steered toward the value stored in the output black level register. The digital black clamp loop is only limited in it’s 2005 National Semiconductor Corporation © range by the offset DAC’s range (see “offset level DAC Range Adjustment on page 21” ...
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... Mnemonic OBL Type: Read/Write Reset Value 0010 0000 Binary Bit Bit Symbol Description [7:0] Black Level 0 - 256 output black level digital code value. 2005 National Semiconductor Corporation © Address Default Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1000 0000 (128d) ...
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... Signed Digital representation of the offset Offset Level level to be applied to the input of the PGA. Please see Figure 11 for details regarding the DAC input format. 2005 National Semiconductor Corporation © Software Control Registers Register Name Even Channel Software Control Address A Hex Mnemonic ...
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... Bias level is relative the value of the binary number stored. [1:0] PGA Stage Adjusts the power level of the 2 Amplifier PGA stage 2 amplifier. The power Bias level is relative the value of the binary number stored. 2005 National Semiconductor Corporation © The The power 17 www.national.com ...
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... SO DATA Figure 14: Serial Interface Read Command Timing t t SENW IH SCLK SEN SI DATA XX 0 CE1 CE0 DATA Figure 15: Serial Interface Write Command Timing 2005 National Semiconductor Corporation © = 10pF, and f L MCLK (Note 7) A Min Conditions note 9 36 40/ MCLK must be active ...
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... Power-On and Reset Timing Details CE1-CE0 Power-On or Reset 2005 National Semiconductor Corporation © Reading the serial registers To read the serial registers, the timing diagram shown in Figure 14 must be met.When SEN is toggled low, and data is loaded as described above in the writing sequence. When SEN toggles high, the new 15 bit word is considered, except this time the read/write bit should indicating a read ...
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... PGA Gain Plots Figure 17: PGA Gain (Linear Scale) vs. PGA Gain Code Figure 18: PGA Gain (Logarithmic Scale) vs. PGA Gain Code 2005 National Semiconductor Corporation © Max. Gain = 20.0 dB PGA Gain Code PGA Gain Code 20 Max. Gain = 10 www.national.com ...
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... DAC input code step. Therefore, the offset DAC is limited to providing offset values less than or equal to ±64 LSB at the ADC output. In some applications, this range of output may 2005 National Semiconductor Corporation © Figure 19: Recommended Layout Pattern not be sufficient possible to increase the range of the DAC by adjusting the DAC reference range ...
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... LM98513. Common Application Pitfalls Driving the inputs (analog or digital) beyond the power supply potential. For proper operation, all input potentials should not be greater than 300mV above that of the power supply not 2005 National Semiconductor Corporation © AV+ VREFT Ladder ...
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... National Semiconductor Corporation © 23 www.national.com ...
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... NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support ...