LM98513CCMTX/NOPB National Semiconductor, LM98513CCMTX/NOPB Datasheet - Page 15

• Manufacturer Part Number: LM98513CCMTX/NOPB
• Description: IC DIGITAL COPIER 10BIT 56TSSOP
• Manufacturer: National Semiconductor

Specifications of LM98513CCMTX/NOPB

• Number Of Bits: 10
• Number Of Channels: 2
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Compliant

Register Memory Map
Register Data
The following section describes all available registers in the
LM98513 register bank and their functions.
PGA Gain Registers
Register Name Even Channel PGA Gain
Address
Mnemonic
Type
Reset Value
Register Name Odd Channel PGA Gain
Address
Mnemonic
Type
Reset Value
Output Black Level Register
Register Name Output Black Level
Address
Mnemonic
Type:
Reset Value
©
2005 National Semiconductor Corporation
[7:0]
[7:0]
[7:0]
Bit
Bit
Bit
Black Level
Bit Symbol
Bit Symbol
Bit Symbol
PGA Gain
PGA Gain
0 Hex
PGAEven
Read/Write
0000 0000 Binary
1 Hex
PGAOdd
Read/Write
0000 0000 Binary.
4 Hex
OBL
Read/Write
0010 0000 Binary
Title
Digital Black Level Clamp Control
Even Channel Software Control
Odd Channel Software Control
Even Channel offset level
Even Channel PGA Gain
Odd Channel offset level
Odd Channel PGA Gain
Power Level Control 0
Power Level Control 1
Analog Input Control
Output Black Level
0.0dB-20.0dB in 0.078dB steps.
0.0dB-20.0dB in 0.078dB steps.
0 - 256 output black level digital
code value.
Test
Test
Test
Test
Test
Description
Description
Description
Figure 12: Register Memory Map
Address
15
Digital Black Level Correction Register
Register Name Digital Black Level Clamp Control
Address
Mnemonic
Type
Reset Value
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
0111
1011
1100
1101
1110
1111
[5:4]
[3:2]
Bit
[6]
[1]
[0]
Auto BLKCLP
DAC Format
Offset Auto-
Generation
Bit Symbol
Integration
Calibration
Averaging
Enable
Enable
Offset
Pulse
Pixel
Default Value
5 Hex
BLKCLP
Read/Write
X101 0011 Binary
1000 0000 (128d)
1000 0000 (128d)
1010 1010 (170d)
X101 0011 (83d)
0010 0000 (32d)
0101 1010 (90d)
XXX0 0000 (0d)
XXX0 0000 (0d)
XX00 0000 (0d)
0000 0000 (0d)
0000 0000 (0d)
n/a
n/a
n/a
n/a
n/a
Alters the format of the DAC
input
information, please see Figure
11.
Black pixels averaged selection:
00
01
10
11
Offset
selection:
00
01
10
11
Enables automatic generation of
the BLKCLP pulse required to
initiate operation of the digital
black level correction loop.
Enables the digital black level
correction loop. Offset level
registers are read-only when
offset
enabled.
32 pixels averaged
Divide-by-16
4 pixels averaged
8 pixels averaged
16 pixels averaged
No Scaling
Divide-by-2
Divide-by-8
registers.
Description
auto-calibration
integration
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