JN5148-001-X NXP Semiconductors, JN5148-001-X Datasheet - Page 48

• Manufacturer Part Number: JN5148-001-X
• Description: IC MCU 802.15.4 32BIT 2.4G 56QFN
• Manufacturer: NXP Semiconductors
• Series: JN5148r

Specifications of JN5148-001-X

• Frequency: 2.4GHz
• Data Rate - Maximum: 667kbps
• Modulation Or Protocol: 802.15.4
• Applications: Home/Building Automation, Industrial Control
• Power - Output: 2.5dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2 V ~ 3.6 V
• Current - Receiving: 17.5mA
• Current - Transmitting: 15mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB RAM, 128kB ROM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 616-1049-2; 935293999531; JN5148-001-X

15 Two-Wire Serial Interface
The JN5148 includes industry standard two-wire synchronous Serial Interface operates as a Master (MSIF) or Slave
(SSIF) that provides a simple and efficient method of data exchange between devices. The system uses a serial data
line (SIF_D) and a serial clock line (SIF_CLK) to perform bi-directional data transfers and includes the following
features:
Common to both master and slave:
Master only:
Slave only:
15.1 Connecting Devices
The clock and data lines, SIF_D and SIF_CLK, are alternate functions of DIO15 and DIO14 respectively. The serial
interface function of these pins is selected when the interface is enabled. They are both bi-directional lines,
connected internally to the positive supply voltage via weak (45kΩ) programmable pull-up resistors. However, it is
recommended that external 4.7kΩ pull-ups be used for reliable operation at high bus speeds, as shown in Figure 35.
When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-
drain or open-collector in order to perform the wired-AND function. The number of devices connected to the bus is
solely dependent on the bus capacitance limit of 400pF.
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Compatible with both I
Support for 7 and 10-bit addressing modes
Optional pulse suppression on signal inputs
Multi-master operation
Software programmable clock frequency
Clock stretching and wait state generation
Software programmable acknowledge bit
Interrupt or bit-polling driven byte-by-byte data-transfers
Bus busy detection
Programmable slave address
Simple byte level transfer protocol
Write data flow control with optional clock stretching or acknowledge mechanism
Read data preloaded or provided as required
JN5148
SIF
DIO14
DIO15
2
C and SMbus peripherals
SIF_CLK
SIF_D
D1_OUT
D1_IN
Figure 35: Connection Details
DEVICE 1
JN-DS-JN5148-001 1v6
CLK1_IN
CLK1_OUT
R
P
R
P
D2_IN
D2_OUT
VDD
Pullup
Resistors
DEVICE 2
CLK2_IN
CLK2_OUT
© NXP Laboratories UK 2010