JN5148/001,515 NXP Semiconductors, JN5148/001,515 Datasheet
JN5148/001,515
Specifications of JN5148/001,515
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JN5148/001,515 Summary of contents
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Data Sheet: JN5148-001 IEEE802.15.4 Wireless Microcontroller Overview The JN5148-001 is an ultra low power, high performance wireless microcontroller targeted at JenNet applications. The device features an enhanced 32-bit RISC processor offering high coding efficiency through variable width instructions, a multi- ...
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Contents 1 Introduction 1.1 Wireless Transceiver 1.2 RISC CPU and Memory 1.3 Peripherals 1.4 Block Diagram 2 Pin Configurations 2.1 Pin Assignment 2.2 Pin Descriptions 2.2.1 Power Supplies 2.2.2 Reset 2.2.3 32MHz Oscillator 2.2.4 Radio 2.2.5 Analogue Peripherals 2.2.6 Digital ...
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Wireless Transceiver 8.1 Radio 8.1.1 Radio External Components 8.1.2 Antenna Diversity 8.2 Modem 8.3 Baseband Processor 8.3.1 Transmit 8.3.2 Reception 8.3.3 Auto Acknowledge 8.3.4 Beacon Generation 8.3.5 Security 8.4 Security Coprocessor 8.5 Location Awareness 8.6 Higher Data Rates 9 ...
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Analogue Peripherals 20.1 Analogue to Digital Converter 20.1.1 Operation 20.1.2 Supply Monitor 20.1.3 Temperature Sensor 20.2 Digital to Analogue Converter 20.2.1 Operation 20.3 Comparators 21 Power Management and Sleep Modes 21.1 Operating Modes 21.1.1 Power Domains 21.2 Active Processing ...
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A.5.2 Reel Information: 180mm Reel A.5.3 Reel Information: 330mm Reel A.5.4 Dry Pack Requirement for Moisture Sensitive Material Appendix B Development Support B.1 Crystal Oscillators B.1.1 Crystal Equivalent Circuit B.1.2 Crystal Load Capacitance B.1.3 Crystal ESR and Required Transconductance B.2 ...
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Introduction The JN5148-001 is an IEEE802.15.4 wireless microcontroller that provides a fully integrated solution for applications using the IEEE802.15.4 standard in the 2.4 - 2.5GHz ISM frequency band [1], including JenNet and ZigBee PRO. It includes all of the ...
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Peripherals The following peripherals are available on chip: • Master SPI port with five select outputs • Two UARTs with support for hardware or software flow control • Three programmable Timer/Counters – all three support Pulse Width Modulation (PWM) ...
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Block Diagram Tick Timer Programmable 32-bit RISC CPU Interrupt Controller Fro m Perip herals RAM ROM 128kB 128kB eFuse VB_XX VDD1 Voltage Regulators VDD2 RESETN Reset Wakeup Timer0 Wakeup Timer1 32kHz Clock Select 32kHz 32kHz RC Clock Osc Gen ...
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Pin Configurations DIO16/RXD 1/IP_DI/JTAG_TDI DIO 16/IP_DI 1 DIO17/CTS1/I P_SEL/DAI_SC K/JTAG _TCK 2 VSS3 3 DIO18/RTS1/IP_INT/DAI_SDOUT/JT AG_TMS 4 DIO19/T XD1/JTAG_TDO 5 VSS2 6 VSSS 7 XTAL_OUT 8 XTAL_IN 9 VB_SYNTH 10 VCOTUNE 11 VB_VCO 12 VDD1 13 IBIAS 14 Figure ...
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Pin Assignment Pin No 10, 12, 16, 18, 27, VB_SYNTH, VB_VCO, VB_RF2, VB_RF, VB_A, VB_RAM, 35, 40 VB_DIG 13, 49 VDD1, VDD2 32 Paddle VSS1, VSS2, VSS3, VSSS, VSSA RESETN 8, 9 XTAL_OUT, ...
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Pin Digital Peripheral I/O No Primary 51 DIO10 TIM0OUT 32KXTALOUT 52 DIO11 TIM1CK_GT 53 DIO12 TIM1CAP 54 DIO13 TIM1OUT 55 DIO14 SIF_CLK 56 DIO15 SIF_D 1 DIO16 IP_DI 2 DIO17 CTS1 4 DIO18 RTS1 5 DIO19 TXD1 31 DIO 20 ...
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Pin Descriptions 2.2.1 Power Supplies The device is powered from the VDD1 and VDD2 pins, each being decoupled with a 100nF ceramic capacitor. VDD1 is the power supply to the analogue circuitry; it should be decoupled to ground. VDD2 ...
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Analogue Peripherals Several of the analogue peripherals require a reference voltage to use as part of their operations. They can use either an internal reference voltage or an external reference connected to VREF. This voltage is referenced to analogue ...
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reset, the digital peripherals are all off and the DIO pins are set as high-impedance inputs. During sleep and deep sleep, the DIO pins retain both their input/output state and output level that was set as sleep ...
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CPU The CPU of the JN5148 is a 32-bit load and store RISC processor. It has been architected for three key requirements: • Low power consumption for battery powered applications • High performance to implement a wireless protocol at ...
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Memory Organisation This section describes the different memories found within the JN5148. The device contains ROM, RAM, OTP eFuse memory, the wireless transceiver and peripherals all within the same linear address space. 4.1 ROM The ROM is 128k bytes ...
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RAM The JN5148 contains 128kBytes of high speed RAM. It can be used for both code and data storage and is accessed by the CPU in a single clock cycle. At reset, a boot loader controls the loading of ...
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At reset, the contents of this memory are copied into RAM by the software boot loader. The Flash memory devices that are supported as standard through the JN5148 bootloader are given in Table 1. Jennic recommends that where possible one ...
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System Clocks Two system clocks are used to provide timing references into the on-chip subsystems of the JN5148. A 16MHz clock, generated by a crystal-controlled 32MHz oscillator, is used by the transceiver, processor, memory and digital and analogue peripherals. ...
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System Clock The 32kHz system clock is used for timing the length of a sleep period (see section 21 Power Management and Sleep Modes) and also to generate the system clock used internally during reset. The clock can ...
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Reset A system reset initialises the device to a pre-defined state and forces the CPU to start program execution from the reset vector. The reset process that the JN5148 goes through is as follows. When power is applied, the ...
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R1 C1 The external resistor and capacitor provide a simple reset operation when connected to the RESETN pin. 6.2 External Reset An external reset is generated by a low level on the RESETN pin. Reset pulses longer than the minimum ...
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Brown-out Detect An internal brown-out detect module is used to monitor the supply voltage to the JN5148; this can be used whilst the device is awake CPU doze mode. Dips in the supply voltage below a ...
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Interrupt System The interrupt system on the JN5148 is a hardware-vectored interrupt system. The JN5148 provides several interrupt sources, some associated with CPU operations (CPU exceptions) and others which are used by hardware in the device. When an interrupt ...
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Hardware Interrupts Hardware interrupts generated from the transceiver, analogue or digital peripherals and DIO pins are individually masked using the Programmable Interrupt Controller (PIC). Management of interrupts is provided in the peripherals library [5]. For details of the interrupts ...
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Wireless Transceiver The wireless transceiver comprises a 2.45GHz radio, modem, a baseband processor, a security coprocessor and PHY controller. These blocks, with protocol software provided as a library, implement an IEEE802.15.4 standards- based wireless transceiver that transmits and receives ...
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Radio External Components In order to realise the full performance of the radio it is essential that the reference PCB layout and BOM are carefully followed. See Appendix B.4. The radio is powered from a number of internal 1.8V ...
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Antenna A SEL ADO (DIO[12]) SELB ADE (DIO[13]) Figure 16 Simple Antenna Diversity Implementation using External RF Switch ADE (DIO[13]) ADO (DIO[12]) TX Active RX Active Figure 17 Antenna Diversity ADO Signal for TX with Acknowledgement If two DIO pins ...
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Modem The modem performs all the necessary modulation and spreading functions required for digital transmission and reception of data at 250kbps in the 2450MHz radio frequency band in compliance with the IEEE802.15.4 standard. It also provides a high data ...
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Baseband Processor The baseband processor provides all time-critical functions of the IEEE802.15.4 MAC layer. Dedicated hardware guarantees air interface timing is precise. The MAC layer hardware/software partitioning, enables software to implement the sequencing of events required by the protocol ...
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During reception, the modem determines the Link Quality, which is made available at the end of the reception as part of the requirements of IEEE802.15.4. 8.3.3 Auto Acknowledge Part of the protocol allows for ...
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Higher Data Rates To support the demands of applications that require high data throughputs such as in audio or data streaming applications, the JN5148 supports higher data rate modes that offer 500kbps or 667kbps on air transmission rates. The ...
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Digital Input/Output There are 21 Digital I/O (DIO) pins, which can be configured as either an input or an output, and each has a selectable internal pull-up resistor. Most DIO pins are multiplexed with alternate peripheral features of the ...
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SPI SPISEL1 Master SPISEL2 SPISEL3 SPISEL4 TXD0 RXD0 UART0 RTS0 CTS0 TXD1 RXD1 UART1 RTS1 CTS1 TIM0CK_GT TIM0OUT Timer0 TIM0CAP TIM1CK_GT TIM1OUT Timer1 TIM1CAP TIM2OUT Timer2 SIF_D 2-wire SIF_CLK Interface IP_DO IP_DI Intelligent IP_INT Peripheral IP_CLK IP_SEL PC0 Pulse PC1 ...
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Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the JN5148 and peripheral devices. The JN5148 operates as a master on the SPI bus and all other devices connected to the SPI are expected ...
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Slave 0 Slave 1 Flash/ User EEPROM Defined Memory SPISEL 0 Figure 24: Typical JN5148 SPI Peripheral Connection The data transfer rate on the SPI bus is determined by the SPICLK signal. The JN5148 supports transfers at selectable data rates ...
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An interrupt can be generated when the transaction has completed or alternatively the interface can be polled slave device wishes to signal the JN5148 indicating that it ...
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Timers 11.1 Peripheral Timer/Counters Three general-purpose timer/counter units are available that can be independently configured to operate in one of five possible modes. Timer 0 and 1 support all 5 modes of operation and Timer 2 supports PWM and ...
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The clock source for the timer unit is fed from the 16MHz system clock. This clock passes to a 5-bit prescaler where a value of 0 leaves the clock unmodified and other values divide applied to ...
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CLK CAPT Rise Fall 11.1.3 Counter/Timer Mode The counter/timer can be used to generate interrupts, based on the timers or event counting, for software to use timer the clock source is from the system clock, prescaled if required. ...
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Conversion cycle 1 Figure 29: Return To Zero Mode in Operation 1 11.1.5 Example Timer / Counter Application Figure 31 shows an application of the JN5148 timers to provide closed loop speed control. Timer 0 is configured ...
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Maskable timer interrupt • Single-shot, Restartable or Continuous modes of operation SysClk & Run The Tick Timer is clocked from a continuous 16MHz clock, which is fed to a 32-bit wide resettable up-counter, gated by ...
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A wakeup timer consists of a 35-bit down counter clocked from the selected 32 kHz clock. An interrupt or wakeup event can be generated when the counter reaches zero. On reaching zero the counter will continue to count down until ...
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Pulse Counters Two 16-bit counters are provided that can increment during all modes of operation (including sleep), based on pulses received on 2 dedicated DIO inputs; DIO1 and DIO8. The pulses can be de-bounced using the 32kHz clock to ...
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Serial Communications The JN5148 has two independent Universal Asynchronous Receiver/Transmitter (UART) serial communication interfaces. These provide similar operating features to the industry standard 16550A device operating in FIFO mode. Each interface performs serial-to-parallel conversion on incoming serial data and ...
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RTS (negated if the receive FIFO fill level is greater than a programmable threshold bytes), and only transmits data when the incoming CTS is asserted. ...
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JTAG Debug Interface The JN5148 includes an IEEE1149.1 compliant JTAG port for the sole purpose of software code debug with Jennic's Software Development Kit. The JTAG interface is disabled by default and is enabled under software control. Therefore, debugging ...
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Two-Wire Serial Interface The JN5148 includes industry standard two-wire synchronous Serial Interface operates as a Master (MSIF) or Slave (SSIF) that provides a simple and efficient method of data exchange between devices. The system uses a serial data line ...
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Clock Stretching Slave devices can use clock stretching to slow down the transfer bit rate. After the master has driven SIF_CLK low, the slave can drive SIF_CLK low for the required period and then release it. If the slave’s ...
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Slave Two-wire Serial Interface When operating as a slave device, the interface does not provide a clock signal, although it may drive the clock signal low required to apply clock stretching. Only transfers whose address matches ...
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Four-Wire Digital Audio Interface The JN5148 includes a four-wire digital audio interface that can be used for interfacing to audio CODECs. The following features are supported: • Compatible with the industry standard I²S interface • Option to support I²S, ...
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Data Buffer SCK WS SD Max Size MSB SD 3-bits L2 Data Buffer SCK WS SD Max Size MSB MSB-1 SD 3-bits L2 L1 Data Buffer SCK WS SD Max Size MSB MSB-1 SD 3-bits Right R2 ...
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Random Number Generator A random number generator is provided which creates a 16-bit random number each time it is invoked. Consecutive calls can be made to build up any length of random number required. Each call takes approximately 0.25msec ...
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Sample FIFO A 10 deep FIFO is provided to buffer data between the CPU and either the four-wire digital audio interface or the DAC/ ADC. It supports single channel input and output data bits wide. When ...
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Intelligent Peripheral Interface The Intelligent Peripheral (IP) Interface is provided for systems that are more complex, where there is a processor that requires a wireless peripheral example, the JN5148 may provide a complete JenNet or ZigBee PRO ...
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If data is queued for transmission and the recipient has indicated that they are ready for it (RXRDY in incoming status byte was 1), the next byte to be transmitted is the data length in words (N). If either the ...
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JN5148. The master must then deassert IP_SEL to show the transfer is complete. The master may initiate a transfer to read data from the JN5148 by asserting the slave select ...
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Analogue Peripherals The JN5148 contains a number of analogue peripherals allowing the direct connection of a wide range of external sensors, switches and actuators. Chip Boundary VREF ADC1 ADC2 ADC3 ADC4 Temp Sensor COMP1P COMP1M COMP2P COMP2M DAC1 DAC2 ...
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Analogue to Digital Converter The 12-bit analogue to digital converter (ADC) uses a successive approximation design to perform high accuracy conversions as typically required in wireless sensor network applications. It has six multiplexed single-ended input channels: four available externally, ...
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Software can then be used to apply the appropriate rounding and shifting to generate the average value, as well as ...
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Comparators The JN5148 contains two analogue comparators COMP1 and COMP2 that are designed to have true rail-to-rail inputs and operate over the full voltage range of the analogue supply VDD1. The hysteresis level (common to both comparators) can be ...
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Power Management and Sleep Modes 21.1 Operating Modes Three operating modes are provided in the JN5148 that enable the system power consumption to be controlled carefully to maximise battery life. • Active Processing Mode • Sleep Mode • Deep ...
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The DAC outputs are placed into a high impedance state. When entering into sleep mode, there is an option to retain the RAM contents throughout the sleep period. If the ...
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Electrical Characteristics 22.1 Maximum Ratings Exceeding these conditions may result in damage to the device. Parameter Device supply voltage VDD1, VDD2 Supply voltage at voltage regulator bypass pins VB_xxx Voltage on analogue pins XTALOUT, XTALIN, VCOTUNE, RF_IN. Voltage on ...
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DC Current Consumption VDD = 2.0 to 3.6V, -40 to +85º C 22.2.2.1 Active Processing Mode: Min CPU processing 32,16,8 or 4MHz Radio transmit Radio receive The following current figures should be added to those above if the feature ...
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I/O Characteristics VDD = 2.0 to 3.6V, -40 to +85º C Parameter Min Internal DIO pullup 22 resistors Digital I/O High Input VDD2 x 0.7 (except DIO9, DIO10) Digital I/O High Input VDD2 x 0.7 ( ...
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RESETN Internal RESET VDD = 2.0 to 3.6V, -40 to +85º C Parameter Min External Reset pulse width to initiate reset sequence (t ) RST External Reset threshold VDD2 x 0.7 voltage (V ) RST Internal Power-on Reset threshold voltage ...
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SPI MasterTiming SS t SSS CLK (mode=0,1) CLK (mode=2,3) MISO (mode=0, MISO (mode=1, MOSI (mode=1,3) MOSI (mode=0,2) Parameter Symbol Clock period t CK Data setup time t SI Data hold time t HI Data invalid ...
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Parameter Clock period Data setup time Data hold time Data invalid period Select set-up period Select hold period Select asserted to output data driven Select negated to data output tri-stated 22.3.4 Two-wire Serial Interface SIF_D LOW SIF_CLK ...
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Four-Wire Digital Audio Interface SCK WS/SDOUT t sr SDIN Parameter DAI_SCK clock period LOW period of the DAI_SCK clock HIGH period of the DAI_SCK clock Transmit delay time Receive set-up time Receive hold time 22.3.6 Wakeup and Boot Load ...
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Bandgap Reference VDD = 2.0 to 3.6V, -40 to +85ºC Parameter Min Voltage 1.156 DC power supply rejection Temperature coefficient Point of inflexion 22.3.8 Analogue to Digital Converters VDD = 3.0V, VREF = 1.2V, -40 to +85ºC Parameter Min ...
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Digital to Analogue Converters VDD = 3.0V, VREF = 1.2V, -40 to +85ºC Parameter Resolution Current consumption Integral nonlinearity Differential nonlinearity Offset error Gain error Internal clock Output settling time to 0.5LSB Minimum Update time Output voltage swing Output ...
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Comparators VDD = 2.0 to 3.6V -40 to +85ºC Parameter Analogue response time (normal) Total response time (normal) including delay to Interrupt controller Analogue response time (low power) Hysteresis Vref (Internal) See Section 22.3.7 Bandgap Reference Common Mode input ...
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Crystal Oscillator VDD = 2.0 to 3.6V, -40 to +85ºC Parameter Min Current consumption of cell and counter logic Start – up time Input capacitance Transconductance External Capacitors (CL=9pF) Amplitude at Xout 22.3.13 32MHz Crystal Oscillator VDD = ...
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RC Oscillator VDD = 2.0 to 3.6V, -40 to +85ºC Parameter Min Current consumption of cell Clock native accuracy -22% Calibrated centre frequency -7% accuracy Variation with temperature Variation with VDD2 Startup time 22.3.15 Temperature Sensor VDD = ...
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Radio Transceiver This JN5148 meets all the requirements of the IEEE802.15.4 standard over 2.0 - 3.6V and offers the following improved RF characteristics. All RF characteristics are measured single ended. This part also meets the following regulatory body approvals, ...
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Radio Parameters: 2.0-3.6V, +25ºC Parameter Min Receive sensitivity -92 Maximum input signal Adjacent channel rejection (-1/+1 ch) [CW Interferer] Alternate channel rejection (- ch) [CW Interferer] Other in band rejection 2.4 to 2.4835 GHz, excluding adj channels Out ...
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Radio Parameters: 2.0-3.6V, -40ºC Parameter Min Receive sensitivity -93.5 Maximum input signal Adjacent channel rejection (-1/+1 ch) [CW Interferer] Alternate channel rejection (- ch) [CW Interferer] Other in band rejection 2.4 to 2.4835 GHz, excluding adj channels Out ...
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Radio Parameters: 2.0-3.6V, +85ºC Parameter Min Receive sensitivity -90 Maximum input signal Adjacent channel rejection (-1/+1 ch) [CW Interferer] Alternate channel rejection (- ch) [CW Interferer] Other in band rejection 2.4 to 2.4835 GHz, excluding adj channels Out ...
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Note1: Blocker rejection is defined as the value, when 1% PER is seen with the wanted signal 3dB above sensitivity, as per 802.15.4 section 6.5.3.4 Note2: Channels 11,17,24 low/high values reversed. Note3 extra 2.5dB of attenuation is ...
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Appendix A Mechanical and Ordering Information A.1 56-pin QFN Package Drawing Figure 51: 56-pin QFN Package Drawings © NXP Laboratories UK 2010 JN-DS-JN5148-001 1v6 Controlling Dimension: mm millimetres Symbol Min. Nom. Max. A ------ ------ 0.9 A1 0.00 0.01 0.05 ...
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A.2 PCB Decal The following PCB decal is recommended; all dimensions are in millimetres (mm). The PCB schematic and layout rules detailed in Appendix B.4 must be followed. Failure will likely result in the JN5148 failing to ...
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A.3 Ordering Information The standard qualification for the JN5148 is Industrial temperature range: -40ºC to +85ºC, packaged in a 56-pin QFN package. Ordering Code Format: JN5148/XXX ROM Variant XXX: 001 Supports all available networking stacks Ordering Codes: Part Number Ordering ...
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A.4 Device Package Marking The diagram below shows the package markings for JN5148. The package on the left along with the legend information below it, shows the general format of package marking. The package on the right shows the specific ...
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A.5 Tape and Reel Information A.5.1 Tape Orientation and Dimensions The general orientation of the 56QFN package in the tape is as shown in Figure 54. Figure 55 shows the detailed dimensions of the tape used for 8x8mm 56QFN devices. ...
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A.5.2 Reel Information: 180mm Reel Surface Resistivity Between 10e Material High Impact Polystyrene, environmentally friendly, recyclable All dimensions and tolerances are fully compliant with EIA-481-B and are specified in millimetres. 6 window design with one window on each side blanked ...
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A.5.3 Reel Information: 330mm Reel Surface Resistivity Between 10e Material High Impact Polystyrene with Antistatic Additive All dimensions and tolerances are fully compliant with EIA-481-B and are specified in millimetres. 3 window design to allow adequate labelling space. Tape Width ...
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Appendix B Development Support B.1 Crystal Oscillators This section covers some of the general background to crystal oscillators, to help the user make informed decisions concerning the choice of crystal and the associated capacitors. B.1.1 Crystal Equivalent Circuit Where C ...
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B.1.3 Crystal ESR and Required Transconductance The resistor in the crystal equivalent circuit represents the energy lost. To maintain oscillation, power must be supplied by the amplifier, but how much? Firstly, the Pi connected capacitors C apply an impedance transformation ...
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B.2 32MHz Oscillator The JN5148 contains the necessary on-chip components to build a 32 MHz reference oscillator with the addition of an external crystal resonator, two tuning capacitors. The schematic of these components are shown in Figure 57. The two ...
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As is stated above, not all combinations of crystal load capacitance and ESR are valid, and as explained in Appendix B.1.3 there is a trade-off that exists between the load capacitance and crystal ESR to achieve reliable performance. For this ...
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B.3 32kHz Oscillator In order to obtain more accurate sleep periods, the JN5148 contains the necessary on-chip components to build an optional 32kHz oscillator with the addition of an external 32.768kHz crystal and two tuning capacitors. The crystal should be ...
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Three examples of typical crystals are given, each with the value of external capacitors to use, plus the likely supply current and start-up time that can be expected. Also given is the maximum recommended ESR based on the start-up criteria ...
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B.4 JN5148 Module Reference Designs For customers wishing to integrate the JN5148 device directly into their system, Jennic provide a range of Module Reference Designs, covering standard and high-power modules fitted with different Antennae To ensure the correct performance, it ...
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Component Value/Type Designator C13 10uF C14 100nF C16 100nF C15 100nF C18 47pF C2 10nF C24 47pF C3 100nF C12 47pF C8 100nF C9 47pF C6 100nF C7 100nF R1 43k C20 100nF U2 4Mbit Y1 32MHz C10 15pF +/-5% ...
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B.4.2 PCB Design and Reflow Profile PCB and land pattern designs are key to the reliability of any electronic circuit design. The Institute for Interconnecting and Packaging Electronic Circuits (IPC) defines a number of standards for electronic devices. One of ...
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Related Documents [1] IEEE Std 802.15.4-2003 IEEE Standard for Information Technology – Part 15.4 Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs). [2] JN-AN-1038 Programming Flash devices not supported by the ...
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Disclaimers The contents of this document are subject to change without notice. Jennic reserves the right to make changes, without notice, in the products, including circuits and/or software, described or contained here in. Information contained in this document regarding device ...
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Contact Details For the contact details of your local Jennic office or distributor, refer to the Jennic web site: © NXP Laboratories UK 2010 NXP Laboratories UK Ltd (Formerly Jennic Ltd) Furnival Street Sheffield S1 4QT United Kingdom Tel: +44 ...