MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 7

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Figure
Number
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
10-1
10-2
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10-4
10-5
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
11-14
11-15
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11-17
11-18
11-19
11-20
11-21
11-22
11-23
11-24
11-25
11-26
11-27
Freescale Semiconductor
SDRAM Timing Register (SDTR)............................................................................................ 9-8
Example Setup Time Violation on SDRAM Data Input during Write ..................................... 9-12
Timing Refinement with Inverted SDCLK.............................................................................. 9-13
Timing Refinement with True CAS Latency and Inverted SDCLK ........................................ 9-13
Timing Refinement with Effective CAS Latency.................................................................... 9-14
SDRAM Burst Read, 32-Bit Port, Page Miss, Access = 9-1-1-1 ........................................... 9-16
SDRAM Burst Read, 32-Bit Port, Page Hit, Access = 5-1-1-1 .............................................. 9-17
SDRAM Burst Write, 32-Bit Port, Page Miss, Access = 7-1-1-1 ........................................... 9-18
SDRAM Burst Write, 32-Bit Port, Page Hit, Access = 3-1-1-1 .............................................. 9-19
SDRAM Refresh Cycle.......................................................................................................... 9-20
Enter SDRAM Self-Refresh Mode......................................................................................... 9-21
Exit SDRAM Self-Refresh Mode ........................................................................................... 9-22
DMA Mode Register (DMR) .................................................................................................. 10-2
DMA Interrupt Register (DIR)................................................................................................ 10-4
DMA Source Address Register (DSAR)................................................................................ 10-5
DMA Destination Address Register (DDAR) ......................................................................... 10-6
DMA Byte Count Register (DBCR) ....................................................................................... 10-6
Ethernet Block Diagram ........................................................................................................ 11-2
Fast Ethernet Module Block Diagram ................................................................................... 11-2
Ethernet Frame Format......................................................................................................... 11-4
Ethernet Address Recognition Flowchart.............................................................................. 11-7
Ethernet Control Register (ECR)......................................................................................... 11-11
Interrupt Event Register (EIR)............................................................................................. 11-12
Interrupt Vector Status Register (IVSR) .............................................................................. 11-14
Receive Descriptor Active Register (RDAR) ....................................................................... 11-15
Transmit Descriptor Active Register (TDAR) ...................................................................... 11-16
MII Management Frame Register (MMFR) ......................................................................... 11-17
FIFO Transmit Start Register (TFSR) ................................................................................. 11-22
Receive Control Register (RCR) ......................................................................................... 11-23
Maximum Frame Length Register (MFLR).......................................................................... 11-24
Transmit Control Register (TCR) ........................................................................................ 11-25
RAM Perfect Match Address Low (MALR).......................................................................... 11-26
RAM Perfect Match Address High (MAUR) ........................................................................ 11-27
Pointer-to-Receive Descriptor Ring (ERDSR)..................................................................... 11-30
Pointer-to-Transmit Descriptor Ring (ETDSR) .................................................................... 11-31
Receive Buffer Size (EMRBR) ............................................................................................ 11-32
Receive Buffer Descriptor (RxBD) ...................................................................................... 11-35
Interrupt Mask Register (EIMR) ......................................................................................... 11-13
MII Speed Control Register (MSCR).................................................................................. 11-18
FIFO Receive Bound Register (FRBR) .............................................................................. 11-19
FIFO Receive Start Register (FRSR)................................................................................. 11-20
Transmit FIFO Watermark (TFWR).................................................................................... 11-21
Hash Table High (HTUR) ................................................................................................... 11-28
Hash Table Low (HTLR) .................................................................................................... 11-29
MCF5272 ColdFire
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Integrated Microprocessor User’s Manual, Rev. 3
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