MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 346

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Queued Serial Peripheral Interface (QSPI) Module
14.4.4
There are two transfer length options. The user can choose a default value of 8 bits or a programmed value
of 8 to 16 bits inclusive. The programmed value must be written into QMR[BITS]. The bits per transfer
enable (BITSE) field in the command RAM determines whether the default value (BITSE = 0) or the
BITS[3–0] value (BITSE = 1) is used. QMR[BITS] gives the required number of bits to be transferred,
with 0b0000 representing 16.
14.4.5
Operation is initiated by setting QDLYR[SPE]. Shortly after QDLYR[SPE] is set, the QSPI executes the
command at the command RAM address pointed to by QWR[NEWQP]. Data at the pointer address in
transmit RAM is loaded into the data serializer and transmitted. Data that is simultaneously received is
stored at the pointer address in receive RAM.
When the proper number of bits has been transferred, the QSPI stores the working queue pointer value in
QWR[CPTQP], increments the working queue pointer, and loads the next data for transfer from the
transmit RAM. The command pointed to by the incremented working queue pointer is executed next
unless a new value has been written to QWR[NEWQP]. If a new queue pointer value is written while a
transfer is in progress, then that transfer is completed normally.
When the CONT bit in the command RAM is set, the QSPI_CS signals are asserted between transfers.
When CONT is cleared, QSPI_CS[0:3] are negated between transfers. The QSPI_CS signals are not high
impedance.
When the QSPI reaches the end of the queue, it asserts the SPIF flag, QIR[SPIF]. If QIR[SPIFE] is set, an
interrupt request is generated when QIR[SPIF] is asserted. Then the QSPI clears QDLYR[SPE] and stops,
unless wraparound mode is enabled.
Wraparound mode is enabled by setting QWR[WREN]. The queue can wrap to pointer address 0x0, or to
the address specified by QWR[NEWQP], depending on the state of QWR[WRTO].
In wraparound mode, the QSPI cycles through the queue continuously, even while requesting interrupt
service. QDLYR[SPE] is not cleared when the last command in the queue is executed. New receive data
overwrites previously received data in the receive RAM. Each time the end of the queue is reached,
QIR[SPIFE] is set. QIR[SPIF] is not automatically reset. If interrupt driven QSPI service is used, the
service routine must clear QIR[SPIF] to abort the current request. Additional interrupt requests during
servicing can be prevented by clearing QIR[SPIFE].
There are two recommended methods of exiting wraparound mode: clearing QWR[WREN] or setting
QWR[HALT]. Exiting wraparound mode by clearing QDLYR[SPE] is not recommended because this may
abort a serial transfer in progress. The QSPI sets SPIF, clears QDLYR[SPE], and stops the first time it
reaches the end of the queue after QWR[WREN] is cleared. After QWR[HALT] is set, the QSPI finishes
the current transfer, then stops executing commands. After the QSPI stops, QDLYR[SPE] can be cleared.
14-8
Transfer Length
Data Transfer
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor