MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 125

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

5.4.1
In the Revision A implementation of the debug module, certain hardware structures are shared between
BDM and breakpoint functionality as shown in
Thus, loading a register to perform a specific function that shares hardware resources is destructive to the
shared function. For example, a BDM command to access memory overwrites an address breakpoint in
ABHR. A BDM write command overwrites the data breakpoint in DBR.
5.4.2
The address attribute trigger register (AATR),
matched in the trigger. The register value is compared with address attribute signals from the processor’s
local high-speed bus, as defined by the setting of the trigger definition register (TDR).
Table 5-5
Freescale Semiconductor
14–13
12–11
10–8
Bits
6–5
15
7
DRc[4–0]
Reset
Name
Field RM
TMM
SZM
TTM
R/W Write only. AATR is accessible in supervisor mode as debug control register 0x06 using the WDEBUG
RM
describes AATR fields.
SZ
R
Revision A Shared Debug Resources
Address Attribute Trigger Register (AATR)
instruction and through the BDM port using the
Register
15
Read/write mask. Setting RM masks R in address comparisons.
Size mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons.
Transfer type mask. Setting a TTM bit masks the corresponding TT bit in address comparisons.
Transfer modifier mask. Setting a TMM bit masks the corresponding TM bit in address comparisons.
Read/write. R is compared with the R/W signal of the processor’s local bus.
Size. Compared to the processor’s local bus size signals.
00 Longword
01 Byte
10 Word
11 Reserved
ABHR
AATR
DBR
14
MCF5272 ColdFire
SZM
Bus attributes for all memory commands
Address for all memory commands
Data for all BDM write commands
Figure 5-5. Address Attribute Trigger Register (AATR)
13
Table 5-4. Rev. A Shared BDM/Breakpoint Hardware
12
TTM
Table 5-5. AATR Field Descriptions
BDM Function
11
®
Integrated Microprocessor User’s Manual, Rev. 3
10
Figure
TMM
0000_0000_0000_0101
Table
WDMREG
5-5, defines address attributes and a mask to be
5-4.
8
Description
0x06
R
7
command.
Attributes for address breakpoint
Address for address breakpoint
Data for data breakpoint
6
SZ
Breakpoint Function
5
4
TT
3
2
TM
Debug Support
0
5-7