MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 52

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

lii
0x00AC
0x00B0
0x00B4
0x00C0
0x00C4
0x00C8
0x00D0
0x00D4
0x00D8
0x00E0
0x00E6
0x00E8
0x00EC
0x00F0
0x0100
0x0104
0x0104
0x0108
0x010C
0x010C
MBAR
MBAR
MBAR
MBAR
Offset
Offset
Offset
Offset
QSPI Interrupt Register
QSPI Address Register
QSPI Data Register
PWM Control Register 0
PWM Control Register 1
PWM Control Register 2
PWM Pulse-Width Register 0
PWM Pulse-Width Register 1
PWM Pulse-Width Register 2
DMA Mode Register
DMA Interrupt Register
DMA Byte Count Register
DMA Source Address Register
DMA Destination Address Register
UART0 Mode Register 1/2
UART0 Status
UART0 Clock Select Register
UART0 Command Register
UART0 Receive Buffer
UART0 Transmit Buffer
MCF5272 ColdFire
Table vii. QSPI Module Memory Map (continued)
Register Name
Register Name
Register Name
Register Name
Table x. UART0 Module Memory Map
Table viii. PWM Module Memory Map
Table ix. DMA Module Memory Map
®
Integrated Microprocessor User’s Manual, Rev. 3
SPINT
SPADDR
SPDATA
PWMCR1
PWMCR2
PWMCR3
PWMWD1
PWMWD2
PWMWD3
DCMR
DCIR
DBCR
DSAR
DDAR
U1MR1/U1MR2
U1SR
U1CSR
U1CR
U1RxB
U1TxB
Old Mnemonic
Old Mnemonic
Old Mnemonic
Old Mnemonic
Freescale Semiconductor
QIR
QAR
QDR
PWCR0
PWCR1
PWCR2
PWWD0
PWWD1
PWWD2
No change
No change
No change
No change
No change
U0MR1/U0MR2
U0SR
U0CSR
U0CR
U0RxB
U0TxB
New Mnemonic
New Mnemonic
New Mnemonic
New Mnemonic