MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 387

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

16.5.3.1
In automatic echo mode, shown in
The local CPU-to-receiver communication continues normally, but the CPU-to-transmitter link is
disabled. In this mode, received data is clocked on the receiver clock and resent on TxD. The receiver must
be enabled, but the transmitter need not be.
Because the transmitter is inactive, USRn[TxEMP,TxRDY] are inactive and data is sent as it is received.
Received parity is checked but is not recalculated for transmission. Character framing is also checked, but
stop bits are sent as they are received. A received break is echoed as received until the next valid start bit
is detected. Autobaud operation does not affect automatic echo mode; that is, the first character received
is correctly echoed back.
16.5.3.2
Figure 16-28
testing the operation of a local UART module channel by sending data to the transmitter and checking data
assembled by the receiver to ensure proper operations.
Features of this local loop-back mode are as follows:
16.5.3.3
In remote loop-back mode, shown in
by bit on the TxD output. The local CPU-to-transmitter link is disabled. This mode is useful in testing
receiver and transmitter operation of a remote channel. For this mode, the transmitter uses the receiver
clock.
Freescale Semiconductor
•
•
•
•
Transmitter and CPU-to-receiver communications continue normally in this mode.
RxD input data is ignored
TxD is held marking
The receiver is clocked by the transmitter clock. The transmitter must be enabled, but the receiver
need not be.
Automatic Echo Mode
Local Loop-Back Mode
shows how TxD and RxD are internally connected in local loop-back mode. This mode is for
Remote Loop-Back Mode
MCF5272 ColdFire
CPU
CPU
Disabled
Figure
Figure 16-28. Local Loop-Back
Figure
Figure 16-27. Automatic Echo
®
Integrated Microprocessor User’s Manual, Rev. 3
16-27, the UART automatically resends received data bit by bit.
16-29, the channel automatically transmits received data bit
Rx
Tx
Rx
Tx
Disabled
Disabled
Disabled
RxD Input
TxD Input
RxD Input
TxD Input
UART Modules
16-27