HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 48

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 2.8
Addressing
Mode
Immediate
addressing
2.3.3
The instruction format refers to the source operand and the destination operand. The meaning of
the operand depends on the instruction code. Symbols are as follows.
Table 2.9
Instruction Formats
0 format
n format
15
15
xxxx
xxxx
xxxx
mmmm
nnnn
iiii
dddd
Instruction Formats
xxxx
nnnn
Addressing Modes and Effective Addresses (cont)
Instruction Formats
Mnemonic
Expression
#imm:8
#imm:8
#imm:8
Instruction code
Source register
Destination register
Immediate data
Displacement
xxxx
xxxx
xxxx
xxxx
Effective Addresses Calculation
The 8-bit immediate data (imm) for the TST, AND,
OR, and XOR instructions are zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD,
and CMP/EQ instructions are sign-extended.
Immediate data (imm) for the TRAPA instruction is
zero-extended and is quadrupled.
0
0
Source
Operand
—
—
Control register
or system
register
Control register
or system
register
Destination
Operand
—
nnnn: Direct
register
nnnn: Direct
register
nnnn: Indirect pre-
decrement register
Instruction
Example
NOP
MOVT
STS
STC.L
Equation
—
—
—
RENESAS25
Rn
MACH,Rn
SR,@-Rn