HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 389

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Receiving Serial Data (asynchronous mode): Figure 13.7 shows a sample flowchart for receiving
serial data. The procedure for receiving serial data is listed below.
1. SCI initialization: select the RxD pin function with the PFC.
2. Receive error handling and break detection: if a receive error occurs, read the ORER, PER and
3. SCI status check and receive data read: read the serial status register (SR), check that RDRF is
4. To continue receiving serial data: read RDRF and RDR, and clear RDRF to 0 before the stop
RENESAS 372
Figure 13.6 Example of SCI Transmit Operation in Asynchronous Mode (8-bit data with
FER bits of the SSR to identify the error. After executing the necessary error handling, clear
ORER, PER and FER all to 0. Receiving cannot resume if ORER, PER or FER remains set to
1. When a framing error occurs, the RxD pin can be read to detect the break state.
set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The
RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt
(RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary.
TDRE
TEND
Serial
data
request
1
TXI
Start
bit
0
handler writes
TXI interrupt
data in TDR
and clears
TDRE to 0
D
0
D
1 frame
1
Data
D
parity and one stop bit)
7
Parity
bit
0/1
request
TXI
Stop
bit
1
Start
bit
0
D
0
D
1
Data
D
7
Parity
bit
0/1
TEI request
Stop
bit
1
Idle (mark
state)
1