HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 113

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

8.1
The bus state controller (BSC) divides address space and outputs control signals for all kinds of
memory and peripheral LSIs. BSC functions enable the LSI to link directly with DRAM, SRAM,
ROM, and peripheral LSIs without the use of external circuits, simplifying system design and
allowing high-speed data transfers in a compact system.
8.1.1
The BSC has the following features.
•
• Direct interface to DRAM
• Access control for all memory and peripheral LSIs
• Parallel execution of external writes and the like with internal access (warp mode)
• Supports parity check and generation for data bus
• Refresh counter can be used as an 8-bit interval timer
8.1.2
Figure 8.1 shows the block diagram of the bus state controller.
Address space is divided into eight areas
A maximum 4-Mbyte of linear address space for each of eight areas, 0–7 (area 1 can be up
Bus width (8 bits or 16 bits) can be selected by access address
On-chip ROM and RAM is accessed in one cycle (32 bits wide)
Wait states can be inserted using the WAIT pin
Wait state insertion can be controlled through software. Register settings can be used to
The type of memory connected can be specified for each area.
Outputs control signals for accessing the memory and peripheral LSIs connected to the area
Multiplexes row/column addresses according to DRAM capacity
Two types of byte access signals (dual-CAS system and dual-WE system)
Supports burst operation (high-speed page mode)
Supports CAS-before-RAS refresh and self-refresh
Address/data multiplex function
Odd parity/even parity selectable
Interrupt request generated for parity error (PEI interrupt request signal)
Interrupt request generated at compare match (CMI interrupt request signal)
to 16-Mbyte linear space when set for DRAM) (The space that can actually be used varies
with the type of memory connected)
specify the insertion of 1–4 cycles for areas 0, 2, and 6 (long wait function)
Overview
Features
Block Diagram
Section 8 Bus State Controller (BSC)
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