HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 163

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Short Pitch High-Speed Page Mode and Long Pitch High-Speed Page Mode: When burst
operation is selected by setting the DCR’s BE bit to 1, the short pitch high-speed page mode or
long pitch high-speed page mode can be selected by setting the RW1, WW1, DRW1, and DWW1
bits of the WCR1 and WCR2.
•
AD15–
Short-pitch, high-speed page mode: When the RW1, WW1, DRW1 and DWW1 bits in the
WCR1 and WCR2 are cleared to 0, and the corresponding DRAM access cycle is continuing,
the CAS signal and column address output cycles continue as long as the row addresses
continue to match. The column address output cycle is performed in 1 state and the WAIT
signal is not sampled. Figure 8.23 shows the read cycle timing for the short pitch high-speed
page mode.
When the write cycle continues for the same row address in the short pitch high-speed page
mode, an open cycle (silent cycle) is produced for 1 cycle only. This timing is shown in figure
8.24. Likewise, when a write cycle continues after the read cycle for the same row address, a
silent cycle is produced for 1 cycle. This timing is shown in figure 8.25. Note also that when
DRAM is written to in short-pitch, high-speed page mode when using DMAC single address
mode, a silent cycle is inserted in each transfer. The details of timing are discussed in section
20.3.3, Bus Timing.
A21–
RAS
CAS
WR
CK
A0
A0
Figure 8.23 Short Pitch High-Speed Page Mode (Read Cycle)
T p
Row address 1
T r
address 1
Column
T c
Data 1
address 2
Column
T c
Data 2
address 3
Column
T c
Data 3
address 4
Column
T c
RENESAS 143
Data 4