HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 406

SH 1 CORE 32B MPU, 20MHZ/5V, 100

HD6417020SX20IV

Manufacturer Part Number
HD6417020SX20IV
Description
SH 1 CORE 32B MPU, 20MHZ/5V, 100
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6417020SX20IV

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Receiving Serial Data (clocked synchronous mode): Figure 13.18 shows a sample flowchart for
receiving serial data. When switching from the asynchronous mode to the clocked synchronous
mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF
bit will not be set and both transmitting and receiving will be disabled. Figure 13.19 shows an
example of SCI recieve operation.
The procedure for recieving serial data is listed below.
1. SCI initialization: select the RxD pin function with the PFC.
2. Receive error handling: if a receive error occurs, read the ORER bit in SSR to identify the
error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving
Figure 13.17 Sample Flowchart for Serial Transmitting
Write transmit data in TDR and
clear TDRE bit to 0 in SSR
Read TDRE bit in SSR
Read TEND bit in SSR
Clear TE bit SCR to 0
All data transmitted?
Transmission ends
Start transmitting
TDRE = 1?
TEND = 1?
Initialize
Yes
Yes
Yes
No
No
No
(1)
(2)
(3)
RENESAS 389

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