HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 141

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Area 1: Area 1 is the area where addresses A26–A24 are 001 and its address range is H'1000000–
H'1FFFFFF and H'9000000–H'9FFFFFF. Figure 8.6 is a memory map of area 1.
Area 1 can be set for use as DRAM space or external memory space with the DRAM enable bit
(DRAME) of the bus control register (BCR). When the DRAME bit is 0, it is external memory
space; when DRAME is 1, it is DRAM space.
In external memory space, the bus width is 8 bits when the A27 bit is 0 and 16 bits when it is 1.
Bits A23 and A22 are not output and the shadow is in 4-Mbyte units. When external memory is
accessed, the CS1 signal is valid.
DRAM space is a type of external memory space, but it is configured especially to be connected to
DRAM so it outputs strobe signals required for this purpose. Its bus width is 8 bits when it is 0 and
16 bits when it is 1. When the multiplex enable bit (MXE) of the DRAM control register (DCR) is
H'8003FFF(SH7020)
H'8007FFF(SH7021)
H'8004000(SH7020)
H'8008000(SH7021)
Note: The bus width of area 0 is determined by the MD2–MD0 pins regardless of the A27 bit
H'8FFC000
H'8FF8000
H'8000000
(SH7020)
(SH7021)
setting.
32-bit space
Logical address space
H'0FFFFFF
H'0FFC000
H'0003FFF
H'0007FFF
H'0FF8000
H'0000000
H'0008000
(SH7020)
(SH7021)
H'004000
(SH7020)
(SH7021)
(SH7020)
(SH7021)
MD2–MD0 = 010
32-bit space
Shadow
Shadow
Shadow
Shadow
Shadow
Shadow
Figure 85 Memory Map of Area 0
• Valid
• CS0 not
On-chip ROM
SH7020:
SH7021:
Actual space
addresses
A15–A0
(A23–A16
ignored)
valid
16 kbyte
32 kbyte
H'8BFFFFF
H'8FFFFFF
H'83FFFFF
H'87FFFFF
H'8C00000
H'8000000
H'8400000
H'8800000
H'0FFFFFF
H'0BFFFFF
H'03FFFFF
H'07FFFFF
H'0C00000
H'0000000
H'0400000
H'0800000
Logical address space
bit space
8 or 16
MD2–MD0 = 000 or 001
Shadow
Shadow
Shadow
Shadow
bit space
8 or 16
RENESAS 121
• MD2–MD0 =
• Valid
• CS0 valid
• Long wait
Actual space
000: 8-bit
access,
001: 16-bit
access
addresses
A21–A0
(A23 and
A22 not
output)
function
(4 Mbytes)
External
memory
space