PIC18F8525-I/PT Microchip Technology, PIC18F8525-I/PT Datasheet - Page 204

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PIC18F8525-I/PT

Manufacturer Part Number
PIC18F8525-I/PT
Description
IC PIC MCU FLASH 24KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F8525-I/PT

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
MSSP, SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
69
Number Of Timers
2 x 8 bit
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163032
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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PIC18F6525/6621/8525/8621
18.4.9
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sam-
pled low, the Baud Rate Generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator count (T
tor times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with the
contents of SSPADD<6:0> and begins counting. SDA
and SCL must be sampled high for one T
action is then followed by assertion of the SDA pin
(SDA = 0) for one T
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the Baud Rate Generator has timed out.
FIGURE 18-20:
DS39612B-page 202
I
START CONDITION TIMING
2
C MASTER MODE REPEATED
RSEN bit set by hardware on the falling
BRG
edge of ninth clock, end of Xmit
BRG
REPEATED START CONDITION WAVEFORM
). When the Baud Rate Genera-
while SCL is high. Following
SDA
SCL
SDA = 1,
SCL (no change).
Write to SSPCON2
occurs here.
BRG
2
C logic
. This
T
SDA = 1,
SCL = 1
BRG
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode, or the default first address in 10-bit mode. After
the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
18.4.9.1
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note:
T
Note 1: If RSEN is programmed while any other
BRG
2: A bus collision during the Repeated Start
Sr = Repeated Start
T
BRG
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
event is in progress, it will not take effect.
condition occurs if:
• SDA is sampled low when SCL goes
• SCL goes low before SDA is
WCOL Status Flag
At completion of Start bit,
hardware clears RSEN bit
from low-to-high.
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
S bit set by hardware
and sets SSPIF
Write to SSPBUF occurs here
T
BRG
 2005 Microchip Technology Inc.
1st bit
T
BRG

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