MC56F8037VLH Freescale Semiconductor, MC56F8037VLH Datasheet - Page 68

• Manufacturer Part Number: MC56F8037VLH
• Description: IC DSP 16BIT DUAL 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8037VLH

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• Package: 64LQFP
• Family Name: 56F8xxx
• Maximum Speed: 32 MHz
• On-chip Adc: 2(8-chx10-bit)
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 5
• For Use With: MC56F8037EVM - BOARD EVAL FOR MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module arbitrates between various interrupt requests (IRQs), signals to
the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to
service this interrupt.
5.2 Features
The ITCN module design includes these distinctive features:
For further information, see
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers that allow each of the 64 interrupt
sources to be set to one of four priority levels (excluding certain interrupts that are of fixed priority). Next,
all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value
of the active interrupt requests for that level. Within a given priority level, number 0 is the highest priority
and number 63 is the lowest.
68
MSCAN_TXFG4
MSCAN_TXFG5
MSCAN_TXFG6
MSCAN_TXFG7
MSCAN_TXFG8
MSCAN_TXFG9
MSCAN_TXFG10
MSCAN_TXFG11
MSCAN_TXFG12
MSCAN_TXFG13
MSCAN_TXFG14
MSCAN_TXFG15
•
•
•
•
Programmable priority levels for each IRQ
Two programmable Fast Interrupts
Notification to SIM module to restart clocks out of Wait and Stop modes
Ability to drive initial address on the address bus after reset
Register Acronym
Table 4-35 MSCAN Registers Address Map (Continued)
Table
4-2, Interrupt Vector Table Contents.
(MSCAN_BASE = $00 F800)
56F8037/56F8027 Data Sheet, Rev. 7
Address Offset
$3A
$3B
$3C
$3D
$3E
$34
$35
$36
$37
$38
$39
$3F
Foreground Transmit Buffer 4
Foreground Transmit Buffer 5
Foreground Transmit Buffer 6
Foreground Transmit Buffer 7
Foreground Transmit Buffer 8
Foreground Transmit Buffer 9
Foreground Transmit Buffer 10
Foreground Transmit Buffer 11
Foreground Transmit Buffer 12
Foreground Transmit Buffer 13
Foreground Transmit Buffer 14
Foreground Transmit Buffer 15
Reserved
Register Description
Freescale Semiconductor