MC56F8037VLH Freescale Semiconductor, MC56F8037VLH Datasheet - Page 110

• Manufacturer Part Number: MC56F8037VLH
• Description: IC DSP 16BIT DUAL 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8037VLH

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• Package: 64LQFP
• Family Name: 56F8xxx
• Maximum Speed: 32 MHz
• On-chip Adc: 2(8-chx10-bit)
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 5
• For Use With: MC56F8037EVM - BOARD EVAL FOR MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

of I/O address, which are “hard coded”. These registers allow access to peripherals using I/O short address
mode, regardless of the physical location of the peripheral, as shown in
With this register set, software can set the SIM_IOSAHI and SIM_IOSALO registers to point to its
peripheral registers and then use the I/O short addressing mode to access them.
Note:
Note:
6.3.13.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.13.2
This field represents the upper two address bits of the “hard coded” I/O short address.
6.3.14
See
110
Section 6.3.13
Base + $10
RESET
Write
Read
The default value of this register set points to the EOnCE registers.
The pipeline delay between setting this register set and using short I/O addressing with the new value
is five instruction cycles.
I/O Short Address Location Register Low (SIM_IOSALO)
Figure 6-15 I/O Short Address Location High Register (SIM_IOSAHI)
Reserved—Bits 15—2
Input/Output Short Address Location (ISAL[23:22])—Bits 1–0
2 bits from SIM_IOSAHI Register
15
Full 24-Bit for Short I/O Address
0
0
for general information about I/O short address location registers.
16 Bits from SIM_IOSALO Register
14
0
0
Figure 6-14 I/O Short Address Determination
13
0
0
6 Bits from I/O Short Address Mode Instruction
12
0
0
56F8037/56F8027 Data Sheet, Rev. 7
11
0
0
10
0
0
“
Hard Coded” Address Portion
9
0
0
8
0
0
7
0
0
6
0
0
5
0
0
Figure
Instruction Portion
4
0
0
6-14.
3
0
0
Freescale Semiconductor
2
0
0
ISAL[23:22]
1
1
0
1