MC56F8037VLH Freescale Semiconductor, MC56F8037VLH Datasheet - Page 65

• Manufacturer Part Number: MC56F8037VLH
• Description: IC DSP 16BIT DUAL 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8037VLH

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• Package: 64LQFP
• Family Name: 56F8xxx
• Maximum Speed: 32 MHz
• On-chip Adc: 2(8-chx10-bit)
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 5
• For Use With: MC56F8037EVM - BOARD EVAL FOR MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
I2C_CTRL
I2C_TAR
I2C_SAR
I2C_DATA
I2C_SSHCNT
I2C_SSLCNT
I2C_FSHCNT
I2C_FSLCNT
I2C_ISTAT
I2C_IMASK
I2C_RISTAT
I2C_RXFT
I2C_TXFT
I2C_CLRINT
I2C_CLRRXUND
I2C_CLRRXOVR
I2C_CLRTXOVR
I2C_CLRRDREQ
I2C_CLRTXABRT
I2C_CLRRXDONE
I2C_CLRACT
I2C_CLRSTPDET
I2C_CLRSTDET
I2C_CLRGC
I2C_ENBL
I2C_STAT
I2C_TXFLR
I2C_RXFLR
I2C_TXABRTSRC
QSPI1_DELAY
Table 4-32 Queued Serial Peripheral Interface 1 Registers Address Map
Register Acronym
Register Acronym
Table 4-33 I
Address Offset
56F8037/56F8027 Data Sheet, Rev. 7
(QSPI1_BASE = $00 F230)
$5
(I2C_BASE = $00 F280)
Address Offset
2
C Registers Address Map
$1A
$1C
$1E
$2A
$2C
$2E
$3A
$3C
$10
$16
$18
$20
$22
$24
$26
$28
$30
$32
$34
$36
$38
$40
$C
$0
$2
$4
$8
$A
$E
Delay Register
Control Register
Target Address Register
Slave Address Register
RX/TX Data Buffer and Command Register
Standard Speed Clock SCL High Count Register
Standard Speed Clock SCL Low Count Register
Fast Speed Clock SCL High Count Register
Fast Speed Clock SCL Low Count Register
Interrupt Status Register
Interrupt Mask Register
Raw Interrupt Status Register
Receive FIFO Threshold Register
Transmit FIFO Threshold Register
Clear Combined and Individual Interrupts Register
Clear RX_UNDER Interrupt Register
Clear RX_OVER Interrupt Register
Clear TX_OVER Interrupt Register
Clear RD_REQ Interrupt Register
Clear TX_ABRT Interrupt Register
Clear RX_DONE Interrupt Register
Clear Activity Interrupt Register
Clear STOP_DET Interrupt Register
Clear START_DET Interrupt Register
Clear GEN_CALL Interrupt Register
Enable Register
Status Register
Transmit FIFO Level Register
Receive FIFO Level Register
Transmit Abort Status Register
Register Description
Register Description
Peripheral Memory-Mapped Registers
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