MC56F8037VLH Freescale Semiconductor, MC56F8037VLH Datasheet
MC56F8037VLH
Specifications of MC56F8037VLH
Available stocks
Related parts for MC56F8037VLH
MC56F8037VLH Summary of contents
Page 1
Data Sheet Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8037 Rev. 7 07/2010 freescale.com ...
Page 2
... Table 10-12 (was “Output frequency after application of 8MHz trim Figure 10-5. 2-3, changed V value from 4.7F to 2.2F. CAP Section 7, Security Features. 56F8037/56F8027 Data Sheet, Rev. 7 (was $00 F060, is $00 F0E0). Table 10-6 as follows: as follows: Table 10-21 (was +/- 20 mV, is ±35 mV). Freescale Semiconductor ...
Page 3
... In the Select Peripheral Input Source for PWM2/PWM3 Pair Source Bits, fixed typos Added new part number to ordering information: MC56F8027MLH Rev. 7 Added MC56F8037MLH to the part ordering table. Please see http://www.freescale.com for the most current data sheet revision. Freescale Semiconductor Document Revision History Description of Change 56F8037/56F8027 Data Sheet, Rev ...
Page 4
... Analog Reg Low-Voltage 16-Bit Supervisor Data ALU Bit -> 36-Bit MAC Manipulation Three 16-bit Input Registers Unit Four 36-bit Accumulators R/W Control System Bus Control XTAL, CLKIN, or System Integration Clock R S Module Generator* EXTAL or GPIOD C *Includes On-Chip Relaxation Oscillator Freescale Semiconductor GPIOD ...
Page 5
... Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.8 Interrupts 129 Part 7 Security Features 129 7.1 Operation with Security Enabled 129 7.2 Flash Access Lock and Unlock Mechanisms130 Freescale Semiconductor 7.3 Product Analysis 131 Part 8 General Purpose Input/Output (GPIO .131 8.1 Introduction 131 8.2 Configuration . . . . . . . . . . . . . . . . . . . . 131 8 ...
Page 6
... Program Flash (56F8027 device) — 8KB of Unified Data/Program RAM (56F8037 device) 4KB of Unified Data/Program RAM (56F8027 device) • EEPROM emulation capability using Flash 6 Table 1-1 Device Differences Feature 56F8037 56F8027 64KB 8KB 56F8037/56F8027 Data Sheet, Rev. 7 32KB 4KB Freescale Semiconductor ...
Page 7
... Two Queued Serial Communication Interfaces (QSCIs) with LIN Slave functionality — Full-duplex or single-wire operation — Two receiver wake-up methods: – Idle line – Address mark — Four-bytes-deep FIFOs are available on both transmitter and receiver • Two Queued Serial Peripheral Interfaces (QSPIs) Freescale Semiconductor 56F8037/56F8027 Data Sheet, Rev. 7 56F8037/56F8027 Features 7 ...
Page 8
... The 56F8037/56F8027 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It combines single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost port 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 9
... PWM, TMR and ADC Connections Figure 1-6 shows the over-limit and under-limit connections from the ADC to the PWM and the Freescale Semiconductor Figures 1-1, 1-2, 1-3, 1-4, 1-5, 1-6, and 1-7. Figures 1-3, 1-4, 1-5, Descriptions, for information about which signals are multiplexed with 56F8037/56F8027 Data Sheet, Rev ...
Page 10
... SYNC0 and TMRA Channel 2 is connected to SYNC1. SYNC0 is the master ADC sync input that is used to trigger ADCA and ADCB in sequence and parallel mode. SYNC1 is used to trigger ADCB in parallel independent mode. These are controlled by bits in the SIM Control Register; see 10 56F8037/56F8027 Data Sheet, Rev. 7 Section 6.3.1. Freescale Semiconductor ...
Page 11
... Program Control Unit PC LA LA2 HWS0 HWS1 FIRA OMR SR LC LC2 FISR Bit- Manipulation Unit Enhanced OnCE™ JTAG TAP Figure 1-1 56800E Core Block Diagram Freescale Semiconductor DSP56800E Core Address Generation Instruction Unit Decoder (AGU) Interrupt M01 Unit N3 Looping Unit ...
Page 12
... To/From IPBus Bridge OCCS (ROSC / PLL / OSC) GPIO A GPIO B GPIO C GPIO D 12 Interrupt Controller Low-Voltage Interrupt POR & LVI System POR SIM COP Reset COP IPBus (Continues on Figure 1-3) Figure 1-2 Peripheral Subsystem 56F8037/56F8027 Data Sheet, Rev. 7 RESET (Muxed with GPIOA7) Freescale Semiconductor ...
Page 13
... INTC PIT0 MSTR_CNT_EN MSTR_CNT_EN PIT1 MSTR_CNT_EN PIT2 2 3 Sync0, Over/Under Sync1 Limits ANA2 (V ADC ANB2 (V Figure 1-3 56F8037/56F8027 I/O Pin-Out Muxing (Part 1/5) Freescale Semiconductor SYNC 3 SYNC SYNC SYNC0, SYNC1 on Figure 1-7 LIMIT on Figure 1-6 ANA0 ANA0 on ) REFHA ANA3 (V ) REFLA ANA4 on ...
Page 14
... TB2, TB3 on Figure 1-5 2 RXD0, TXD0 2 TA2, TA3 on Figure 1-7 MISO0, MOSI0 2 SCLK0, SS0 SCL, SDA 2 2 CANTX, CANRX 2 2 ANA4, ANB4 on Figure 1-3 TXD1, RXD1 2 56F8037/56F8027 Data Sheet, Rev. 7 GPIOB4 3 GPIOA12 - GPIOB6 - 7 GPIOB2 - 3 GPIOB0 - 1 GPIOB8 - 9 2 GPIOB12 - 13 2 GPIOC8 - 12 Freescale Semiconductor ...
Page 15
... CMP_OUT CMP_IN2 Export Import DAC0 DAC1 Import Export CMP_IN2 CMP_OUT CMPB CMP_IN3 CMP_IN1 IPBus Figure 1-5 56F8037/56F8027 I/O Pin-Out Muxing (Part 3/5) Freescale Semiconductor FAULT1 on Figure 1-6 TA2 on Figure 1-7 CMPAI1 CMPAI3 CMPAO on Figure 1-6, Figure 1-7 CMPAI2 ANA0 on Figure 1-3 ...
Page 16
... Figure 1-7 3 56F8037/56F8027 Data Sheet, Rev. 7 GPIOA6 GPIOA0 - 3 GPIOA4 - FAULT1 on Figure 1-5 CMPAO on Figure 1-5 FAULT2 on Figure 1-5 CMPBO on Figure 1-5 GPIOB5 CMPBO on Figure 1-5 CMPAO on Figure 1-5 3 GPIOB2 - 4 on Figure 1-4 3 LIMIT on Figure 1-3 3 TA0o, TA2o, TA3o on Figure 1-3 Freescale Semiconductor ...
Page 17
... To/From IPBus Bridge T0o T0i T1o T1i TMRA T2o T2i T3o T3i IPBus Figure 1-7 56F8037/56F8027 I/O Pin-Out Muxing (Part 5/5) Freescale Semiconductor TA0o on TA0 on TA0 on TA1 on TA1 on CMPAO on SYNC1 on TA2o on TA2 on TA2 on TA2 on TA2 on CMPBO on SYNC0 on TA3o on TA3 on TA3 on TA3 on ...
Page 18
... Product Documentation The documents listed in Table 1-2 56F8037/56F8027. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: http://www.freescale.com Table 1-2 56F8037/56F8027 Chip Documentation Topic DSP56800E Detailed description of the 56800E family architecture, Reference Manual ...
Page 19
... Queued Serial Communications Interface 0 (QSCI0) Ports Queued Serial Communications Interface 1 (QSCI1) Ports Inter-Integrated Circuit Interface (I 1 MSCAN Ports 1 Oscillator Signals JTAG/Enhanced On-Chip Emulation (EOnCE) 1. Pins may be shared with other peripherals. See Freescale Semiconductor Table 2-2, each table row describes the signal or Functional Group ) DDA ) 1 1 ...
Page 20
... ANB5 ANB2 V REFHB ANB3 V REFLB ANA3 V REFLA ANA2 V REFHA ANA5 ANA1 ANA6 ANA0 ANA7 TXD1 ANA4 56F8037/56F8027 Data Sheet, Rev. 7 Power & DAC Comp MSCAN JTAG Ground CMPBI1 CMPBI2 CMPBI3 DAC1 V DDA V SSA DAC0 CMPAI3 V SS Freescale Semiconductor Misc. CLKIN CLKIN ...
Page 21
... DD 51 VSS GPIOD5 GPIOD5, XTAL, CLKIN D5 53 GPIOD4 GPIOD4, EXTAL D4 54 GPIOB8 GPIOB8, SCL, CANTX B8 55 GPIOA1 GPIOA1, PWM1 A1 Freescale Semiconductor Quad I2C QSCI QSPI ADC PWM Timer TB0 MOSI0 PSRC1 TA3 MISO0 PSRC0 TA2 FAULT0 TA0 TB2 FAULT1 TA2 SCLK1 ...
Page 22
... GPIOC14, ANB6 C14 63 TMS TMS, GPIOD3 D3 64 TDO TDO, GPIOD1 D1 22 Quad I2C QSCI QSPI ADC PWM Timer PWM0 TB1 ANB7 ANB6 56F8037/56F8027 Data Sheet, Rev. 7 Power & DAC Comp MSCAN JTAG Ground CANTX CANRX TD1 CMPBO TMS TDO Freescale Semiconductor Misc. ...
Page 23
... GPIOB5 (TA1, FAULT3, CLKIN) or TMRA or TMRB GPIOB6 (RXD0, SDA, CLKIN) or QSPI1 or GPIOB GPIOB7 (TXD0, SCL) DAC GPIOD6-7 (DAC0-1) or GPIOD TDI (GPIOD0) TDO (GPIOD1) JTAG/ EOnCE TCK (GPIOD2) or GPIOD TMS (GPIOD3) Figure 2-1 56F8037/56F8027 Signals Identified by Functional Group Freescale Semiconductor DDA SSA 1 1 ...
Page 24
... Port A GPIO — This GPIO pin can be individually programmed as an input or open drain output pin. Note that RESET functionality is disabled in this mode and the chip can only be reset via POR, COP reset, or software reset. After reset, the default state is RESET. 56F8037/56F8027 Data Sheet, Rev. 7 Signal Description 10.2.1. Freescale Semiconductor ...
Page 25
... Output GPIOA3 48 Input/ Output (PWM3) Output Return to Table 2-2 Freescale Semiconductor State During Reset Input, Port A GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pull-up enabled PWM0 — This is one of the six PWM output pins. After reset, the default state is GPIOA0. ...
Page 26
... Fault2 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. After reset, the default state is GPIOA5. The peripheral functionality is controlled via the SIM. See 56F8037/56F8027 Data Sheet, Rev. 7 Signal Description Section 6.3.16. Section 6.3.16. Freescale Semiconductor ...
Page 27
... Input (TA3) Input/ Output (CMPBI1) Input Return to Table 2-2 Freescale Semiconductor State During Reset Input, Port A GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pull-up enabled Fault0 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. TA0 — ...
Page 28
... A Schmitt trigger input is used for noise immunity. TB1 — Timer B, Channel 1. TA1 — Timer A, Channel 1. After reset, the default state is GPIOA12. The peripheral functionality is controlled via the SIM. See 56F8037/56F8027 Data Sheet, Rev. 7 Signal Description Section 6.3.16. Section 6.3.16. Section 6.3.16. Freescale Semiconductor ...
Page 29
... The TB3 signal is also brought out on the GPIOA11 pin. 13 The TA3 signal is also brought out on the GPIOA5, GPIOA9, and GPIOB3 pins. Return to Table 2-2 Freescale Semiconductor State During Reset Input, Port A GPIO — This GPIO pin can be individually programmed as internal an input or output pin. ...
Page 30
... QSPI0 module that the current transfer received. Serial Data — This pin serves as the I After reset, the default state is GPIOB1. The peripheral functionality is controlled via the SIM. See 56F8037/56F8027 Data Sheet, Rev. 7 Signal Description 2 C serial clock. Section 6.3.16 serial data line. Section 6.3.16. Freescale Semiconductor ...
Page 31
... Output Input (PSRC1) 17 The TA3 signal is also brought out on the GPIOA5, GPIOA9 and GPIOA14 pins. Return to Table 2-2 Freescale Semiconductor State During Reset Input, Port B GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pull-up enabled QSPI0 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device ...
Page 32
... External Clock Input— This pin serves as an external clock input. After reset, the default state is GPIOB5. The peripheral functionality is controlled via the SIM. See 56F8037/56F8027 Data Sheet, Rev. 7 Signal Description Section 6.3.7. Section 6.3.16. Section 6.3.16. Freescale Semiconductor ...
Page 33
... The SCL signal is also brought out on the GPIOB0 and GPIOB7 pins. 24 The CANTX signal is also brought out on the GPIOB12 pin. Return to Table 2-2 Freescale Semiconductor State During Reset Input, Port B GPIO — This GPIO pin can be individually programmed as internal an input or output pin. ...
Page 34
... TB1— Timer B, Channel 1. Comparator B Output— This is the output of comparator B. After reset, the default state is GPIOB11. The peripheral functionality is controlled via the SIM. See 56F8037/56F8027 Data Sheet, Rev. 7 Signal Description 2 C serial data line. Section 6.3.16. Section 6.3.16. Section 6.3.16. Freescale Semiconductor ...
Page 35
... Input (V ) Analog REFHA Input Return to Table 2-2 Freescale Semiconductor State During Reset Input Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. CAN Transmit Data — This is the MSCAN interface output. After reset, the default state is GPIOB12. ...
Page 36
... Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB2 — Analog input to ADC B, Channel 2. V — Analog reference voltage high (ADC B). REFHx After reset, the default state is GPIOC6. 56F8037/56F8027 Data Sheet, Rev. 7 Signal Description Freescale Semiconductor ...
Page 37
... Input/ Output (ANA7) Analog Input Return to Table 2-2 Freescale Semiconductor State During Reset Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB3 — Analog input to ADC B, Channel 3. V — Analog reference voltage low (ADC B). ...
Page 38
... External Crystal Oscillator Input — This input can be connected to an 8MHz external crystal. Tie this pin low if XTAL is being driven by an external clock source. After reset, the default state is GPIOD4. 56F8037/56F8027 Data Sheet, Rev. 7 Signal Description Freescale Semiconductor ...
Page 39
... Output (GPIOD1) Input/ Output Return to Table 2-2 Freescale Semiconductor State During Reset Input Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. External Crystal Oscillator Output — This output connects the internal crystal oscillator output to an external crystal. ...
Page 40
... TCK and has an on-chip pull-up resistor. enabled Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TMS. Note: Always tie the TMS pin to V 56F8037/56F8027 Data Sheet, Rev. 7 Signal Description through a 2.2K resistor. DD Freescale Semiconductor ...
Page 41
... Control Register (OCCS_CTRL) • Divide-by Register (OCCS_DIVBY) • Status Register (OCCS_STAT) • Shutdown Register (OCCS_SHUTDN) • Oscillator Control Register (OCCS_OCTRL) For more information on these registers, please refer to the 56F802x and 56F803x Peripheral Reference Manual. Freescale Semiconductor 56F8037/56F8027 Data Sheet, Rev. 7 Features 41 ...
Page 42
... The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. 42 Figure 3-1 56F8037/56F8027 Data Sheet, Rev. 7 shows a typical crystal oscillator Freescale Semiconductor ...
Page 43
... External Clock Input - Crystal Oscillator Option The recommended method of connecting an external clock is illustrated in source is connected to XTAL and the EXTAL pin is grounded. The external clock input must be generated using a relatively low impedance driver. Freescale Semiconductor Sample External Crystal Parameters 750 K ...
Page 44
... On-chip memory sizes for the device are summarized in identified in the “Use Restrictions” column of 44 56F8037/56F8027 CLKMODE = 1 XTAL EXTAL External GND or Clock GPIO 56F8037/56F8027 GPIO External Clock Table Table 4-1. 56F8037/56F8027 Data Sheet, Rev. 7 Figure 3-3. The external clock 4-1. Flash memories’ restrictions are Freescale Semiconductor ...
Page 45
... Freescale Semiconductor 56F8027 16k x 16 Erase / Program via Flash interface unit and word writes to CDBW or 32KB Usable by both the Program and Data memory spaces or 4KB Vector Base Address + P:$00 Reserved for Reset Overlay ...
Page 46
... QSCI1 Receiver Full P:$ Error P:$ General P:$ Receive P:$ Transmit P:$ Status P:$5A Timer A, Channel 0 P:$5C Timer A, Channel 1 P:$5E Timer A, Channel 2 P:$60 Timer A, Channel 3 P:$62 Timer B, Channel 0 P:$64 Timer B, Channel 1 P:$66 Timer B, Channel 2 P:$68 Timer B, Channel 3 56F8037/56F8027 Data Sheet, Rev (Continued) Interrupt Function Freescale Semiconductor ...
Page 47
... P: $1F FFFF P: $00 9000 P: $00 8FFF P: $00 8000 P: $00 7FFF P: $00 0000 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Data space starting at address X: $00 0000; see Freescale Semiconductor Vector Base Address + P:$6A Comparator A P:$6C Comparator B P:$6E Interval Timer 0 ...
Page 48
... Internal Program Flash 32KB Cop Reset Address = $00 4002 Boot Location = $00 4000 RESERVED Memory Allocation EOnCE 256 locations allocated RESERVED On-Chip Peripherals 4096 locations allocated RESERVED RESERVED RESERVED On-Chip Data RAM 2 8KB 56F8037/56F8027 Data Sheet, Rev. 7 Figure 4-2. 1 Figure 4-1. Freescale Semiconductor ...
Page 49
... X:$00 8000 X:$00 7FFF X:$00 0800 X:$00 07FF X:$00 0000 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Program space starting at P: $00 8000; see Freescale Semiconductor Dual Port RAM Memory Allocation EOnCE 256 locations allocated RESERVED On-Chip Peripherals 4096 locations allocated ...
Page 50
... Trace Buffer Pointer Register Trace Buffer Register Stages Breakpoint Unit Control Register Breakpoint Unit Control Register Breakpoint Unit Address Register 1 Breakpoint Unit Address Register 1 Breakpoint Unit Address Register 2 56F8037/56F8027 Data Sheet, Rev. 7 Data EOnCE Reserved Peripherals Reserved RAM Register Name Freescale Semiconductor ...
Page 51
... CLK, PLL, OSC Power Supervisor GPIO Port A GPIO Port B GPIO Port C GPIO Port D PIT 0 PIT 1 PIT 2 Freescale Semiconductor Breakpoint Unit Address Register 2 Breakpoint Unit Mask Register 2 Breakpoint Unit Mask Register 2 Reserved EOnCE Breakpoint Unit Counter Reserved Reserved Reserved External Signal Control Register ...
Page 52
... X:$00 F1F0 QSCI0 X:$00 F200 QSCI1 X:$00 F210 QSPI0 X:$00 F220 QSPI1 X:$00 F230 I2C X:$00 F280 FM X:$00 F400 CAN X:$00 F800 56F8037/56F8027 Data Sheet, Rev. 7 Table Number 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 Freescale Semiconductor ...
Page 53
... TMRA1_HOLD TMRA1_CNTR TMRA1_CTRL TMRA1_SCTRL TMRA1_CMPLD1 TMRA1_CMPLD2 TMRA1_CSCTRL TMRA1_FILT TMRA2_COMP1 TMRA2_COMP2 TMRA2_CAPT TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCTRL TMRA2_CMPLD1 Freescale Semiconductor (TMRA_BASE = $00 F000) Address Offset Register Description $0 Compare Register 1 $1 Compare Register 2 $2 Capture Register $3 Load Register $4 Hold Register $5 Counter Register $6 Control Register ...
Page 54
... Control Register $7 Status and Control Register $8 Comparator Load Register 1 $9 Comparator Load Register 2 $A Comparator Status and Control Register $B Input Filter Register Reserved $F Timer Channel Enable Register $10 Compare Register 1 $11 Compare Register 2 $12 Capture Register 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 55
... TMRB2_SCTRL TMRB2_CMPLD1 TMRB2_CMPLD2 TMRB2_CSCTRL TMRB2_FILT TMRB3_COMP1 TMRB3_COMP2 TMRB3_CAPT TMRB3_LOAD TMRB3_HOLD TMRB3_CNTR TMRB3_CTRL TMRB3_SCTRL TMRB3_CMPLD1 TMRB3_CMPLD2 TMRB3_CSCTRL TMRB3_FILT Freescale Semiconductor (TMRB_BASE = $00 F040) Address Offset Register Description $13 Load Register $14 Hold Register $15 Counter Register $16 Control Register $17 Status and Control Register $18 Comparator Load Register 1 $19 ...
Page 56
... Result Register 15 $1C Low Limit Register 0 $1D Low Limit Register 1 $1E Low Limit Register 2 $1F Low Limit Register 3 $20 Low Limit Register 4 $21 Low Limit Register 5 $22 Low Limit Register 6 $23 Low Limit Register 7 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 57
... Register Acronym PWM_CTRL PWM_FCTRL PWM_FLTACK PWM_OUT PWM_CNTR PWM_CMOD PWM_VAL0 PWM_VAL1 PWM_VAL2 PWM_VAL3 PWM_VAL4 PWM_VAL5 PWM_DTIM0 Freescale Semiconductor (ADC_BASE = $00 F080) Address Offset Register Description $24 High Limit Register 0 $25 High Limit Register 1 $26 High Limit Register 2 $27 High Limit Register 3 $28 High Limit Register 4 ...
Page 58
... Fast Interrupt Vector Address Low 0 Register $A Fast Interrupt Vector Address High 0 Register $B Fast Interrupt Match 1 Register $C Fast Interrupt Vector Address Low 1 Register $D Fast Interrupt Vector Address High 1 Register $E IRQ Pending Register 0 $F IRQ Pending Register 1 $10 IRQ Pending Register 2 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 59
... SIM_PCR SIM_PCE0 SIM_PCE1 SIM_SD0 SIM_SD1 SIM_IOSAHI SIM_IOSALO SIM_PROT SIM_GPSA0 SIM_GPSA1 SIM_GPSB0 SIM_GPSB1 SIM_GPSCD SIM_IPS0 SIM_IPS1 SIM_IPS2 Freescale Semiconductor (ITCN_BASE = $00 F0E0) Address Offset Register Description $11 IRQ Pending Register 3 Reserved $16 Interrupt Control Register Reserved (SIM_BASE = $00 F100) Register Description $0 Control Register $1 Reset Status Register ...
Page 60
... Address Offset Register Description $0 Control Register $1 Status Register Reserved (GPIOA_BASE = $00 F150) Address Offset $0 Pull-up Enable Register $1 Data Register $2 Data Direction Register $3 Peripheral Enable Register $4 Interrupt Assert Register $5 Interrupt Enable Register $6 Interrupt Polarity Register 56F8037/56F8027 Data Sheet, Rev. 7 Register Description Freescale Semiconductor ...
Page 61
... Register Acronym GPIOC_PUPEN GPIOC_DATA GPIOC_DDIR GPIOC_PEREN GPIOC_IASSRT GPIOC_IEN GPIOC_IPOL GPIOC_IPEND GPIOC_IEDGE GPIOC_PPOUTM GPIOC_RDATA GPIOC_DRIVE Freescale Semiconductor (GPIOA_BASE = $00 F150) Address Offset Register Description $7 Interrupt Pending Register $8 Interrupt Edge-Sensitive Register $9 Push-Pull Output Mode Control Register $A Raw Data Input Register $B Output Drive Strength Control Register ...
Page 62
... F190) Address Offset Register Description $0 Control Register $1 Modulo Register $2 Counter Register (PIT1_BASE = $00 F1A0) Address Offset Register Description $0 Control Register $1 Modulo Register $2 Counter Register (PIT2_BASE = $00 F1B0) Address Offset Register Description $0 Control Register $1 Modulo Register 56F8037/56F8027 Data Sheet, Rev. 7 Register Description Freescale Semiconductor ...
Page 63
... DAC1_MAXVAL Table 4-27 Comparator A Registers Address Map Register Acronym CMPA_CTRL CMPA_STAT CMPA_FILT Table 4-28 Comparator B Registers Address Map Register Acronym CMPB_CTRL CMPB_STAT CMPB_FILT Freescale Semiconductor (PIT2_BASE = $00 F1B0) Address Offset Register Description $2 Counter Register (DAC0_BASE = $00 F1C0) Address Offset Register Description $0 Control Register ...
Page 64
... Data Receive Register $3 Data Transmit Register $4 FIFO Control Register $5 Delay Register (QSPI1_BASE = $00 F230) Address Offset Register Description $0 Status and Control Register $1 Data Size and Control Register $2 Data Receive Register $3 Data Transmit Register $4 FIFO Control Register 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 65
... I2C_CLRRXUND I2C_CLRRXOVR I2C_CLRTXOVR I2C_CLRRDREQ I2C_CLRTXABRT I2C_CLRRXDONE I2C_CLRACT I2C_CLRSTPDET I2C_CLRSTDET I2C_CLRGC I2C_ENBL I2C_STAT I2C_TXFLR I2C_RXFLR I2C_TXABRTSRC Freescale Semiconductor (QSPI1_BASE = $00 F230) Address Offset Register Description $5 Delay Register 2 C Registers Address Map (I2C_BASE = $00 F280) Address Offset $0 Control Register $2 Target Address Register $4 Slave Address Register ...
Page 66
... Transmitter Flag Register $07 Transmitter Interrupt Enable Register $08 Transmitter Message Abort Request Register $09 Transmitter Message Abort Acknowledge Register $0A Transmitter Buffer Selection Register $0B Identifier Acceptance Control Register Reserved $0D Miscellaneous Register $0E Receive Error Register $0F Transmit Error Register 56F8037/56F8027 Data Sheet, Rev. 7 Register Description Freescale Semiconductor ...
Page 67
... MSCAN_RXFG6 MSCAN_RXFG7 MSCAN_RXFG8 MSCAN_RXFG9 MSCAN_RXFG10 MSCAN_RXFG11 MSCAN_RXFG12 MSCAN_RXFG13 MSCAN_RXFG14 MSCAN_RXFG15 MSCAN_TXFG0 MSCAN_TXFG1 MSCAN_TXFG2 MSCAN_TXFG3 Freescale Semiconductor (MSCAN_BASE = $00 F800) Address Offset $10 Identifier Acceptance Register 0 $11 Identifier Acceptance Register 1 $12 Identifier Acceptance Register 2 $13 Identifier Acceptance Register 3 $14 Identifier Mask Register 0 $15 Identifier Mask Register 1 ...
Page 68
... Foreground Transmit Buffer 9 $3A Foreground Transmit Buffer 10 $3B Foreground Transmit Buffer 11 $3C Foreground Transmit Buffer 12 $3D Foreground Transmit Buffer 13 $3E Foreground Transmit Buffer 14 $3F Foreground Transmit Buffer 15 Reserved 4-2, Interrupt Vector Table Contents. 56F8037/56F8027 Data Sheet, Rev. 7 Register Description Freescale Semiconductor ...
Page 69
... Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes Fast Interrupts before the core does. A Fast Interrupt is defined (to the ITCN) by: 1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers 2. Setting the FIMn register to the appropriate vector number Freescale Semiconductor Exceptions Permitted 0 Priorities ...
Page 70
... Priority Level 2 -> 4 INT1 Decode Priority Level 2 -> 4 INT64 Decode Figure 5-1 Interrupt Controller Block Diagram 70 any0 Level 0 64 -> Priority Encoder any3 Level 3 64 -> Priority Encoder 56F8037/56F8027 Data Sheet, Rev. 7 Fast Interrupt INT VAB CONTROL IPIC IACK SR[9:8] PIC_EN Freescale Semiconductor ...
Page 71
... IRQP0 $E IRQP1 $F IRQP2 $10 IRQP3 $11 ICTRL $16 Freescale Semiconductor Table 5-3 ITCN Register Summary (ITCN_BASE = $00 F0E0) Register Name Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Priority Register 3 Interrupt Priority Register 4 Interrupt Priority Register 5 Interrupt Priority Register 6 Vector Base Address Register ...
Page 72
... ADCB_CC ADC_ZC IPL ADCA_CC IPL IPL 0 0 FAST INTERRUPT FAST INTERRUPT 0 VECTOR ADDRESS HIGH 0 0 FAST INTERRUPT FAST INTERRUPT 1 VECTOR ADDRESS HIGH INT_ DIS Freescale Semiconductor 1 0 STPCNT IPL FM_ERR IPL GPIOC IPL QSCI0_TIDL IPL I2C_GEN IPL TMRB_0 IPL PIT2 IPL ...
Page 73
... This field is used to set the interrupt priority level for the EOnCE Receive Register Full IRQ. This IRQ is limited to priorities 1 through disabled by default. • IRQ disabled (default) • IRQ is priority level 1 • IRQ is priority level 2 • IRQ is priority level 3 Freescale Semiconductor LVI IPL RX_REG IPL ...
Page 74
... This field is used to set the interrupt priority level for the EOnCE Step Counter IRQ. This IRQ is limited to priorities 1 through disabled by default. • IRQ disabled (default) • IRQ is priority level 1 • IRQ is priority level 2 • IRQ is priority level 3 74 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 75
... MSCAN Receive Interrupt Priority Level (MSCAN_RX IPL)—Bits 9–8 This field is used to set the interrupt priority level for MSCAN Receive IRQ. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 Freescale Semiconductor MSCAN_TX MSCAN_RX ...
Page 76
... This field is used to set the interrupt priority level for the FM Error IRQ. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 76 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 77
... IRQ is priority level 1 • IRQ is priority level 2 5.6.3.4 QSPI 0 Transmitter Empty Interrupt Priority Level (QSPI0_XMIT IPL)— Bits 9–8 This field is used to set the interrupt priority level for the QSPI0 Transmitter Empty IRQ. This IRQ is limited to priorities 0 through disabled by default. Freescale Semiconductor QSPI1_RCV ...
Page 78
... This field is used to set the interrupt priority level for the GPIOC IRQ. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 78 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 79
... QSCI 1 Transmitter Idle Interrupt Priority Level (QSCI1_TIDL IPL)— Bits 9–8 This field is used to set the interrupt priority level for the QSCI1 Transmitter Idle IRQ. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 Freescale Semiconductor QSCI1_RER QSCI1_TIDL QSCI1_XMIT ...
Page 80
... This field is used to set the interrupt priority level for the QSCI0 Transmitter Idle IRQ. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 80 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 81
... This field is used to set the interrupt priority level for the Timer A, Channel 1 IRQ. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor TMRA_1 IPL TMRA_0 IPL I2C_STAT IPL ...
Page 82
... It is disabled by default. • IRQ disabled (default) • IRQ is priority level Status IRQ. This IRQ is limited to priorities 2 C Transmit IRQ. This IRQ is limited Receiver IRQ. This IRQ is limited General Call IRQ. This IRQ is limited to 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 83
... This field is used to set the interrupt priority level for the Comparator B IRQ. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor COMPB IPL COMPA IPL TMRB_3 IPL ...
Page 84
... Timer B, Channel 0 Interrupt Priority Level (TMRB_0 IPL)—Bits 1–0 This field is used to set the interrupt priority level for the Timer B, Channel 0 IRQ. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 84 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 85
... This field is used to set the interrupt priority level for the ADC Zero Crossing IRQ. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor PWM_F IPL PWM_RL IPL ...
Page 86
... The 56F8037 resets to a value of 0x0000. This corresponds to reset addresses of 0x000000. The 56F8027 resets to a value of 0x0080. This corresponds to reset addresses of 0x004000. Figure 5-10 Vector Base Address Register (VBA) 5.6.8.1 Reserved—Bits 15–14 This bit field is reserved. Each bit must be set VECTOR_BASE_ADDRESS 56F8037/56F8027 Data Sheet, Rev Freescale Semiconductor 0 0 ...
Page 87
... Figure 5-12 Fast Interrupt 0 Vector Address Low Register (FIVAL0) 5.6.10.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0 The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. Freescale Semiconductor ...
Page 88
... Fast Interrupt 1 Vector Address Low Register (FIVAL1) Base + $ Read Write RESET Figure 5-15 Fast Interrupt 1 Vector Address Low Register (FIVAL1 FAST INTERRUPT 1 VECTOR ADDRESS LOW 56F8037/56F8027 Data Sheet, Rev FAST INTERRUPT 0 VECTOR ADDRESS HIGH FAST INTERRUPT Freescale Semiconductor ...
Page 89
... This register bit values represent the pending IRQs for interrupt vector numbers 2 through 16. Ascending IRQ numbers correspond to ascending bit locations. • IRQ pending for this vector number • IRQ pending for this vector number 5.6.15.2 Reserved—Bit 0 This bit field is reserved. It must be set to 0. Freescale Semiconductor ...
Page 90
... This register bit values represent the pending IRQs for interrupt vector numbers 49 through 63. Ascending IRQ numbers correspond to ascending bit locations. • IRQ pending for this vector number • IRQ pending for this vector number PENDING[32:17 PENDING[48:33 PENDING[63:49 56F8037/56F8027 Data Sheet, Rev Freescale Semiconductor ...
Page 91
... This read-only field shows bits [7:1] of the Vector Address Bus used at the time the last IRQ was taken. In the case of a Fast Interrupt, it shows the lower address bits of the jump address. This field is only updated when the 56800E core jumps to a new interrupt service routine. Freescale Semiconductor 12 11 ...
Page 92
... SIM. The reset vector will be presented until the second rising clock edge after RESET is released. The general timing is shown in RES CLK VAB PAB 92 Table 5-5 Reset Summary Priority Source RST Figure 5-22. RESET_VECTOR_ADR Figure 5-22 Reset Interface 56F8037/56F8027 Data Sheet, Rev. 7 Characteristics Core reset from the SIM READ_ADR Freescale Semiconductor ...
Page 93
... The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The System Integration Module’s functions are discussed in more detail in the following sections. Freescale Semiconductor 56F8037/56F8027 Data Sheet, Rev. 7 Introduction ...
Page 94
... Peripheral protection control to provide runaway code protection for safety-critical applications • Controls output of internal clock sources to CLKO pin • Four general-purpose software control registers are reset only at power-on • Peripherals Stop mode clocking control 94 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 95
... GPSB0 $15 GPSB1 $16 GPSCD $17 IPS0 $18 IPS1 $19 IPS2 $1A Freescale Semiconductor Register Name Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half of JTAG ID Least Significant Half of JTAG ID Power Control Register Reserved CLKO Select Register ...
Page 96
... TA3_ TA2_ TA1_ ISAL[23:22 PCEP GPS_ GPS_ GPS_A9 A11 A10 0 GPS_ GPS_B3 GPS_B2 GPS_ GPS_ GPS_ B10 GPS_ GPS_ C12 C8 IPS0_PSRC1 IPS0_PSRC0 0 0 IPS1_DSYNC1 IPS1_DSYNC0 Freescale Semiconductor 1 0 WAIT_ DISABLE LRSTDBY PWM TA0 0 PWM_ SD TA0_ SD GIPSP 0 0 GPS_A8 0 GPS_ B0 0 GPS_ ...
Page 97
... Wait mode will be entered when the 56800E core executes a WAIT instruction and the WAIT_DISABLE field is write-protected until the next reset • The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is write-protected until the next reset Freescale Semiconductor ...
Page 98
... External Reset (EXTR)—Bit 3 When set, this bit indicates that the previous system reset was caused by an external reset. 6.3.2.6 Power-On Reset (POR)—Bit 2 This bit is set during a Power-On Reset 56F8037/56F8027 Data Sheet, Rev COP_ COP_ SWR EXTR POR 0 TOR LOR Freescale Semiconductor ...
Page 99
... Figure 6-5 Most Significant Half of JTAG ID (SIM_MSHID) 6.3.5 Least Significant Half of JTAG ID (SIM_LSHID) This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $801D. Base + $ Read Write RESET Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID) Freescale Semiconductor Software Control Data ...
Page 100
... GPIOB4 can function as GPIO other peripheral outputs, including clock output (CLKO). If GPIOB4 is programmed to operate as a peripheral output and CLKO is selected in the SIM_GPSB0 register, bits [4:0] decide if CLKO is enabled or disabled and which clock source is selected if CLKO is enabled. See Figure 6-8 for details. 100 56F8037/56F8027 Data Sheet, Rev LRSTDBY Freescale Semiconductor 0 0 ...
Page 101
... I/O cell. CLKO may not operate as expected when CLKDIS and CLKOSEL settings are changed. • 00000 = Continuous system clock • 00001 = Continuous peripheral clock • 00010 = 3X system clock • 00100.....11111 = Reserved for factory test Freescale Semiconductor ...
Page 102
... C module run clock rate equals the system clock rate maximum 32MHz (default) 2 • module run clock rate equals 3X system clock rate maximum 96MHz 6.3.8.5 Reserved—Bits 11–0 This bit field is reserved. Each bit must be set to 0. 102 I2C_ run clock. 56F8037/56F8027 Data Sheet, Rev Freescale Semiconductor ...
Page 103
... The clock is enabled to the DAC0 module 6.3.9.5 Reserved—Bit 11 This bit field is reserved. It must be set to 0. 6.3.9.6 Analog-to-Digital Converter Clock Enable (ADC)—Bit 10 • The clock is not provided to the ADC module (the ADC module is disabled) • The clock is enabled to the ADC module Freescale Semiconductor ...
Page 104
... Peripheral Clock Enable registers. Base + $ Read 0 PIT2 PIT1 Write RESET Figure 6-11 Peripheral Clock Enable Register 1 (SIM_PCE1) 104 module (the I C module is disabled module PIT0 TB3 56F8037/56F8027 Data Sheet, Rev TB2 TB1 TB0 TA3 TA2 TA1 Freescale Semiconductor 0 TA0 0 ...
Page 105
... The clock is enabled to the Timer A3 module 6.3.10.11 Quad Timer A, Channel 2 Clock Enable (TA2)—Bit 2 • The clock is not provided to the Timer A2 module (the Timer A2 module is disabled) • The clock is enabled to the Timer A2 module Freescale Semiconductor 56F8037/56F8027 Data Sheet, Rev. 7 Register Descriptions 105 ...
Page 106
... The clock is disabled during Stop mode • The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 106 DAC0_ ADC_ 56F8037/56F8027 Data Sheet, Rev I2C_ QSCI1 QSCI0 QSPI1 QSPI0 SD _SD _SD _SD _SD Freescale Semiconductor 0 PWM_ SD 0 ...
Page 107
... The clock is disabled during Stop mode • The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.12 QSPI0 Clock Stop Disable (QSPI0_SD)—Bit 2 Each bit controls clocks to the indicated peripheral. Freescale Semiconductor 56F8037/56F8027 Data Sheet, Rev. 7 Register Descriptions 107 ...
Page 108
... The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.5 Reserved—Bits 11–8 This bit field is reserved. Each bit must be set to 0. 108 PIT0_ TB3_ 56F8037/56F8027 Data Sheet, Rev TB2_ TB1_ TB0_ TA3_ TA2_ TA1_ Freescale Semiconductor 0 TA0_ SD 0 ...
Page 109
... In I/O short address mode, the instruction specifies only 6 LSBs of the effective address; the upper 18 bits are “hard coded” specific area of memory. This scheme allows efficient access to a 64-location area in peripheral space with single word instruction. Short address location registers specify the upper 18 bits Freescale Semiconductor 56F8037/56F8027 Data Sheet, Rev. 7 Register Descriptions ...
Page 110
... I/O Short Address Location Register Low (SIM_IOSALO) See Section 6.3.13 for general information about I/O short address location registers. 110 “ Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction 56F8037/56F8027 Data Sheet, Rev. 7 Figure 6-14. Instruction Portion ISAL[23:22 Freescale Semiconductor 0 1 ...
Page 111
... Peripheral Clock Enable Protection (PCEP)—Bits 3–2 These bits enable write protection of all fields in the PCEn, SDn, and PCR registers in the SIM module. • Write protection off (default) • Write protection on • Write protection off and locked until chip reset Freescale Semiconductor ISAL[21:6] ...
Page 112
... The GPSn setting can be altered during normal operation, but a delay must be inserted between the time when one function is disabled and another function is enabled. 112 GPIOA6_PEREN GPIOA6 0 1 Table 2-3. 56F8037/56F8027 Data Sheet, Rev. 7 Figure 6-18 illustrates the output path to Register 0 GPIOA6 pin 1 Freescale Semiconductor ...
Page 113
... TA2 - Timer A2 • Reserved 6.3.16.5 Reserved—Bits 7–0 This bit field is reserved. Each bit must be set to 0. 6.3.17 SIM GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1) See Section 6.3.16 for general information about GPIO Peripheral Select Registers. Freescale Semiconductor GPS_A5 GPS_A4 0 ...
Page 114
... This bit field is reserved. It must be set to 0. 6.3.17.6 Configure GPIOA11 (GPS_A11)—Bit 6 This field selects the alternate function for GPIOA11. • CMPBI2 - Comparator B Input 2 (default) • TB3 - Timer B3 114 GPS_A13 GPS_A12 56F8037/56F8027 Data Sheet, Rev GPS_ GPS_ GPS_A9 GPS_A8 A11 A10 Freescale Semiconductor 0 0 ...
Page 115
... Figure 6-21 GPIO Peripheral Select Register 0 for GPIOB (SIM_GPSB0) 6.3.18.1 Reserved—Bit 15 This bit field is reserved. It must be set to 0. 6.3.18.2 Configure GPIOB6 (GPS_B6)—Bits 14–13 This field selects the alternate function for GPIOB6. • RXD0 - QSCI0 Receive Data (default) • SDA - I2C Serial Data Freescale Semiconductor GPS_B5 GPS_B4 GPS_B3 0 ...
Page 116
... TA2 - Timer A2 • PSRC0 - PWM0 / PWM1 Pair External Source • Reserved 6.3.18.7 Reserved—Bit 3 This bit field is reserved. It must be set to 0. 6.3.18.8 Configure GPIOB1 (GPS_B1)—Bit 2 This field selects the alternate function for GPIOB1. 116 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 117
... Reserved—Bit 7 This bit field is reserved. It must be set to 0. 6.3.19.4 Configure GPIOB10 (GPS_B10)—Bit 6 This field selects the alternate function for GPIOB10. • CMPAO - Comparator A Output (default) • TB0 - Timer B0 6.3.19.5 Reserved—Bit 5 This bit field is reserved. It must be set to 0. Freescale Semiconductor ...
Page 118
... GPIO Peripheral Select Registers. Base + $ Read Write RESET Figure 6-23 GPIO Peripheral Select Register for GPIOC and GPIOD (SIM_GPSCD) 6.3.20.1 Reserved—Bits 15–13 This bit field is reserved. Each bit must be set to 0. 118 GPS_ 56F8037/56F8027 Data Sheet, Rev GPS_ GPS_ C12 Freescale Semiconductor ...
Page 119
... I/O pin as the source, then GPSn register settings must configure only one I/O pin to feed this peripheral input function. Also, the GPIOx_PEREN bit for that I/O pin must be set enable peripheral control of the I/O. Freescale Semiconductor 56F8037/56F8027 Data Sheet, Rev. 7 Register Descriptions ...
Page 120
... I/O pin (External) - Use PWM FAULT2 Input Pin (default) • CMPAO (Internal) - Use Comparator A Output 120 SIM_GPSA0 Register PWM5 00 01 Timer A3 10 Comparator A Output (Internal IPS0_ IPS0_PSRC2 FAULT1 56F8037/56F8027 Data Sheet, Rev. 7 GPIOA5_PEREN Register GPIOA5 0 GPIOA5 pin IPS0_PSRC1 IPS0_PSRC0 Freescale Semiconductor ...
Page 121
... Reserved • 1x1 = Reserved 6.3.21.8 Select Peripheral Input Source for PWM0/PWM1 Pair Source (IPS0_PSRC0)—Bits 2–0 This field selects the alternate input source signal to feed PWM input PSRC0 as the PWM0/PWM1 pair source. Freescale Semiconductor 56F8037/56F8027 Data Sheet, Rev. 7 Register Descriptions 121 ...
Page 122
... TA0 (Internal) - Use Timer A0 output as DAC SYNC input • 101 = TA1 (Internal) - Use Timer A1 output as DAC SYNC input • 11x = Reserved 6.3.22.3 Reserved—Bit 3 This bit field is reserved. It must be set to 0. 122 56F8037/56F8027 Data Sheet, Rev IPS1_DSYNC1 IPS1_DSYNC0 Freescale Semiconductor 0 0 ...
Page 123
... This bit field is reserved. Each bit must be set to 0. 6.3.23.4 Select Peripheral Input Source for TA2 (IPS2_TA2)—Bit 8 This field selects the alternate input source signal to feed Quad Timer A, input 2. • I/O pin (External) - Use Timer A2 input/output pin • CMPBO (Internal) - Use Comparator B output Freescale Semiconductor ...
Page 124
... Manual for further details. The peripheral clock enable controls can be used to disable an individual peripheral clock when it is not used. 6.5 Power-Saving Modes The 56F8037/56F8027 operates in one of five Power-Saving modes, as shown in 124 2 C modules. These clocks are generated by 56F8037/56F8027 Data Sheet, Rev. 7 Section 6.5), clock enables, . Table 6-2 Freescale Semiconductor ...
Page 125
... Stop mode. By asserting a peripheral’s Stop disable bit, the peripheral clock continues to operate in Stop mode. This is useful to generate interrupts which will recover the device from Stop mode to Run mode. Standby mode provides normal operation but at very low speed and power utilization Freescale Semiconductor Peripheral Clocks Peripheral clocks ...
Page 126
... Stretched version of POR released 64 OSC_CLK cycles after POR deasserts Released 32 OSC_CLK cycles after all reset sources, including EXTENDED_POR, have released Releases 32 SYS_CLK cycles after the CLKGEN_RST is released Releases 32 SYS_CLK cycles after PERIP_RST is released 6-3. Note that the POR_Delay blocks Freescale Semiconductor 6.3.1, ...
Page 127
... The SIM is responsible for clock distributions. While the SIM generates the ADC peripheral clock in the same way it generates all other peripheral clocks, the ADC standby and conversion clocks are generated by a direct interface between the ADC and the OCCS module. Freescale Semiconductor EXTENDED_POR CLKGEN_RST COMBINED_RST ...
Page 128
... CORE_RST. Both PERIP_RST and CORE_RST should be released on the negative edge of SYS_CLK_D as shown. This phased releasing of system resets is necessary to give some peripherals (for example, the Flash interface unit) set-up time prior to the 56800E core becoming active. 128 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 129
... Refer to the flash memory chapter in the 56F802x and 56F803x Peripheral Reference Manual for the details. When flash security mode is enabled, the 56F8037/56F8027 will disable the core EOnCE debug capabilities. Normal Freescale Semiconductor for Combined reset extension Switch on falling OSC_CLK ...
Page 130
... After completing the programming, both the JTAG TAP controller and the device must be reset in order to return to normal unsecured operation. Power-on reset will also reset both. 130 sequence via JTAG, 56F8037/56F8027 Data Sheet, Rev. 7 the JTAG public instruction Freescale Semiconductor ...
Page 131
... Pins in GPIO Port 56F8037/56F 8027 Freescale Semiconductor Table 8-1. The specific mapping of GPIO port pins is shown Tables 2-2 and 2-3. Table 8-1 GPIO Ports Configuration Peripheral Function PWM, Timer, QSPI, Comparator, Reset 2 QSPI PWM, Clock, MSCAN, Comparator, Timer ADC, Comparator, QSCI Clock, Oscillator, DAC, JTAG 56F8037/56F8027 Data Sheet, Rev ...
Page 132
... SIM register SIM_GPS is used to select between SCLK1, TB1, and TA1. Defaults to A12 44 SIM register SIM_GPS is used to select between MISO1, TB2, and TA2. Defaults to A13 45 SIM register SIM_GPS is used to select between MOSI1, TB3, and TA3. Defaults to A14 56F8037/56F8027 Data Sheet, Rev. 7 Notes Freescale Semiconductor ...
Page 133
... GPIOB6 RXD0 / SDA / CLKIN GPIOB7 TXD0 / SCL GPIOB8 SCL / CANTX GPIOB9 SDA / CANRX GPIOB10 TB0 / CMPAO Freescale Semiconductor LQFP Package Pin 42 SIM register SIM_GPS is used to select between SCLK and SCL. Defaults SIM register SIM_GPS is used to select between SS0 and SDA. Defaults to B1 ...
Page 134
... Defaults to C7 SIM register SIM_GPS is used to select between ANA4 and TXD1. Defaults to C8 Defaults to C9 Defaults to C10 Defaults to C11 SIM register SIM_GPS is used to select between ANB4 and RXD1. Defaults to C12 Defaults to C13 Defaults to C14 Defaults to C15 Defaults to TDI Defaults to TDO Freescale Semiconductor ...
Page 135
... XTAL / CLKIN GPIOD6 DAC0 GPIOD7 DAC1 8.3 Reset Values Tables 8-1 and 8-2 detail registers for the 56F8037/56F8027; Figures maps and reset values. Freescale Semiconductor LQFP Package Pin 29 Defaults to TCK 63 Defaults to TMS 53 Defaults SIM register SIM_GPSCD is used to select between XTAL and CLKIN. ...
Page 136
... GPIOA_DDIR GPIOA_PEREN GPIOA_IASSRT GPIOA_IEN GPIOA_IEPOL GPIOA_IPEND GPIOA_IEDGE GPIOA_PPOUTM GPIOA_RDATA GPIOA_DRIVE Figure 8-1 GPIOA Register Map Summary 136 RAW DATA[15: Read as 0 Reserved Reset 56F8037/56F8027 Data Sheet, Rev PU[15: D[15: DD[15: PE[15: IA[15: IEN[15: IEPOL[15: IPR[15: IES[15: OEN[15: DRIVE[15: Freescale Semiconductor ...
Page 137
... Add. Register Acronym 15 Offset GPIOB_PUPEN GPIOB_DATA GPIOB_DDIR GPIOB_PEREN GPIOB_IASSRT GPIOB_IEN GPIOB_IEPOL GPIOB_IPEND GPIOB_IEDGE GPIOB_PPOUTM GPIOB_RDATA GPIOB_DRIVE Figure 8-2 GPIOB Register Map Summary Freescale Semiconductor RAW DATA[15: Read as 0 Reserved Reset 56F8037/56F8027 Data Sheet, Rev. 7 Reset Values PU[15: D[15: DD[15: PE[15: IA[15:0] ...
Page 138
... R $2 GPIOC_DDIR GPIOC_PEREN GPIOC_IASSRT GPIOC_IEN GPIOC_IEPOL GPIOC_IPEND GPIOC_IEDGE GPIOC_PPOUTM GPIOC_RDATA GPIOC_DRIVE Figure 8-3 GPIOC Register Map Summary 138 PU[15: D[15: DD[15: PE[15: IA[15: IEN[15: IEPOL[15: IPR[15: IES[15: OEN[15: RAW DATA[15: DRIVE[15: Read as 0 Reserved Reset 56F8037/56F8027 Data Sheet, Rev Freescale Semiconductor ...
Page 139
... Add. Register Acronym 15 Offset R $0 GPIOD_PUPEN GPIOD_DATA GPIOD_DDIR GPIOD_PEREN GPIOD_IASSRT GPIOD_IEN GPIOD_IEPOL GPIOD_IPEND GPIOD_IEDGE GPIOD_PPOUTM GPIOD_RDATA GPIOD_DRIVE Figure 8-4 GPIOD Register Map Summary Freescale Semiconductor Read as 0 Reserved Reset 56F8037/56F8027 Data Sheet, Rev. 7 Reset Values PU[15: D[15: DD[15: PE[15: IA[15: IEN[15:0] ...
Page 140
... Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either 140 are stress ratings only, and functional operation at the maximum = 3.0–3.6V, CL < 50pF 32MHz OP CAUTION of any voltages 56F8037/56F8027 Data Sheet, Rev the package. DD higher than or DD Freescale Semiconductor ...
Page 141
... Continuous clamp current per pin is -2.0 mA Default Mode Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: RESET, GPIOA7 Pin Group 3: ADC and Comparator Analog Inputs Pin Group 4: XTAL, EXTAL Pin Group 5: DAC Analog Outputs Freescale Semiconductor ( 0V) SS SSA Symbol ...
Page 142
... useful value to use to estimate junction temperature in steady state customer 56F8037/56F8027 Data Sheet, Rev. 7 Typ Max Unit — — V — — V — — Value Unit Notes (LQFP) 41 °C °C °C °C °C °C °C/W 5 Freescale Semiconductor ...
Page 143
... Ambient Operating Temperature (Extended Industrial) Flash Endurance (Program Erase Cycles) Flash Data Retention Flash Data Retention with <100 Program/Erase Cycles 1. Total chip source or sink current cannot exceed 75mA Note: Pin groups are detailed following Freescale Semiconductor ( 0V, V REFL x SSA Symbol Notes V DD, ...
Page 144
... Max Unit Conditions — — — 0 A 0 +/- 2 5.5V A 0 +/- A 0 +/- A V -30 -60 0 +/- 2.5 A 0 +/- 2 V A 0 +/- 2 V — Typically DDA 40mV A 0 +/- 2.5 0.35 — — — pF Freescale Semiconductor Test = I OHmax = I OLmax = 2. DDA = V DDA = — — — — — ...
Page 145
... Clock ADC/DAC/Comparator powered off STOP 4MHz Device Clock Relaxation Oscillator on PLL powered off Processor Core in STOP state All peripheral module and core clocks are off ADC/DAC/Comparator powered off Freescale Semiconductor 1.5 2.0 2.5 3.0 3.5 Volt /I vs. V (Typical; Pull-Up Disabled) ...
Page 146
... Data Sheet, Rev. 7 Typical @ 3.3V, 25°C Maximum@ 3.6V, 25° DDA DD DD 540A 0A 650A 440A 0A 550A Typ Max Unit Min 2.58 2.7 — V — 2.15 — V — 50 — mV — 1.8 1.9 V Freescale Semiconductor I DDA 1A 1A ...
Page 147
... Data Valid state, when a signal level has reached V • Data Invalid state, when a signal level is in transition between V Data1 Valid Data1 Data Invalid State Data Active Freescale Semiconductor pin. The specifications for this regulator are shown in Table 10-8. Regulator Parameters Symbol Min I — ...
Page 148
... rise t fall t PW – Figure 10-4 External Clock Timing 56F8037/56F8027 Data Sheet, Rev. 7 Typ Max — 40 — — — — 1 Typ Max — — — — 3 — — 3 90% 50% 10 fall rise Freescale Semiconductor Unit Unit MHz ...
Page 149
... Variation over temperature -40C to 150ºC Variation over temperature 0C to 105ºC 1. Output frequency after factory trim. 2. This is the time required from Standby to Normal mode transition required to meet QSCI requirements See Figure 10-5 Freescale Semiconductor Table 10-11 PLL Timing Symbol 1 4 Symbol Minimum 1 f — ...
Page 150
... Figure 10-5 Relaxation Oscillator Temperature Variation (Typical) After Trim 150 Degrees C (Junction) 56F8037/56F8027 Data Sheet, Rev. 7 100 125 150 175 Freescale Semiconductor ...
Page 151
... Parameters listed are guaranteed by design. 3. During Power-On Reset possible to use the 56F8037/56F8027 internal reset stretching circuitry to extend this period to 2^21T. GPIO pin (Input) Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive) Freescale Semiconductor Reset, Stop, Wait, Mode Select, and Interrupt Timing Symbol Typical Min t 4T ...
Page 152
... Freescale Semiconductor ...
Page 153
... SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) t MISO (Input) MOSI (Output) Figure 10-7 SPI Master Timing (CPHA = 0) Freescale Semiconductor SS is held High on master MSB in Bits 14– Master MSB out Bits 14– 56F8037/56F8027 Data Sheet, Rev. 7 Serial Peripheral Interface (SPI) Timing LSB in ...
Page 154
... SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 10-8 SPI Master Timing (CPHA = 1) 154 SS is held High on master MSB in Bits 14– Master MSB out Bits 14– 56F8037/56F8027 Data Sheet, Rev LSB in t (ref Master LSB out t R Freescale Semiconductor ...
Page 155
... SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-9 SPI Slave Timing (CPHA = 0) Freescale Semiconductor ELD Slave MSB out Bits 14– MSB in Bits 14–1 56F8037/56F8027 Data Sheet, Rev. 7 Serial Peripheral Interface (SPI) Timing ELG Slave LSB out ...
Page 156
... Slave MSB out Bits 14– MSB in Bits 14–1 Table 10-15 Timer Timing Symbol Min INHL P 125 OUT P 50 OUTHL 56F8037/56F8027 Data Sheet, Rev ELG Slave LSB out LSB Max Unit See Figure — ns 10-11 — ns 10-11 — ns 10-11 — ns 10-11 Freescale Semiconductor ...
Page 157
... Timer Inputs Timer Outputs Freescale Semiconductor P P INHL OUTHL OUT Figure 10-11 Timer Timing 56F8037/56F8027 Data Sheet, Rev. 7 Quad Timer Timing P INHL P OUTHL 157 ...
Page 158
... Figure 10-12 RXD Pulse Width TXD PW Figure 10-13 TXD Pulse Width 56F8037/56F8027 Data Sheet, Rev Max Unit See Figure (f /16) Mbps — MAX 1.04/BR ns 10-12 1.04/BR ns 10- — — — Master — node bit periods — Slave node — bit periods Freescale Semiconductor ...
Page 159
... C bus HD; DAT devices Data set-up time t SU; DAT Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Freescale Semiconductor Freescale’s Scalable Controller Area Network (MSCAN) Timing Table 10-17 MSCAN Timing Symbol Min BR — CAN T T WAKEUP ...
Page 160
... SU; DAT t SU; STA t SR HIGH 56F8037/56F8027 Data Sheet, Rev. 7 Fast Mode Unit Minimum Maximum s 0.6 — s 1.3 — the SCL signal. LOW >= 250ns SU; DAT 2 C bus specification) before the SCL line BUF HD; STA SP t SU; STO Bus Freescale Semiconductor S ...
Page 161
... TCK frequency of operation must be less than 1/8 the processor rate. TCK (Input – Figure 10-16 Test Clock Input Timing Diagram TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) Figure 10-17 Test Access Port Timing Diagram Freescale Semiconductor Table 10-19 JTAG Timing Symbol Min Max f DC SYS_CLK — — ...
Page 162
... AIC +/- 3 +/- 5 +/- .6 +/- 1 GUARANTEED +/- 4 +/- 9 +/- 6 +/- 12 1.01 to .99 — V REFH — V DDA 0 +/- 2 0 — — 3 Figure 10-18 — Figure 10-18 — 10.0 Freescale Semiconductor Unit Bits MHz V 3 cycles 3 cycles 3 cycles 3 cycles 5 LSB 5 LSB mV mV — A Ohms Bits ...
Page 163
... Comparator (CMP) Parameters Parameter Conditions/Comments 1 Within range of V Input Offset Voltage Input Propagation Delay Power-up time 1. No guaranteed specification within 0. Freescale Semiconductor - while the other charges to the analog input voltage. When REFLx 125 ESD Resistor 8pF noise damping capacitor ...
Page 164
... TBD — 500.000 conv/sec — — 11 — +/- 3 +/- 8.0 — +/- .8 < guaranteed — +/- 25 +/- 40 — +/- .5 +/- 1.5 — V REFLX REFHX - .04V — 70 100 — — TBD — — TBD — 9 — — Freescale Semiconductor Unit bits µS µS 2 LSB 2 LSB — bits ...
Page 165
... I/O cells as a function of capacitive load. In these cases: TotalPower = ((Intercept + Slope*Cload)*frequency/10MHz) where: • Summation is performed over all output pins with capacitive loads • TotalPower is expressed in mW • Cload is expressed in pF Freescale Semiconductor 2 *F CMOS power dissipation corresponding to the Intercept 1.3 0.11mW / pF 1.15mW 0.11mW / pF Table 10-23 provides coefficients for calculating power dissipated 56F8037/56F8027 Data Sheet, Rev ...
Page 166
... For instance, if there is a total of eight PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored assumed to be negligible. 166 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 167
... GPIOC13 / ANB5 GPIOC6 / ANB2 / V REFHB GPIOC7 / ANB3 / V REFLB GPIOD7 / DAC1 V DDA Figure 11-1 Top View, 56F8037/56F8027 64-Pin LQFP Package Freescale Semiconductor Figure 11-1 shows the package outline, Table 11-1 lists the pin-out. Orientation Mark 17 56F8037/56F8027 Data Sheet, Rev. 7 56F8037/56F8027 Package and Pin-Out Information ...
Page 168
... Data Sheet, Rev. 7 Pin Signal Name # 49 V CAP GPIOD5 XTAL / CLKIN 53 GPIOD4 EXTAL 54 GPIOB8 SCL / CANTX 55 GPIOA1 PWM1 V 56 GPIOA0 SS PWM0 V 57 GPIOB12 DD CANTX 58 GPIOB13 CANRX 59 TDI GPIOD0 60 GPIOB11 TB1 / CMPBO 61 GPIOC15 ANB7 62 GPIOC14 ANB6 63 TMS GPIOD3 64 TDO GPIOD1 Freescale Semiconductor 1 ...
Page 169
... H A VIEW D1/2 D SEATING C PLANE 60X VIEW Y Figure 11-2 56F8037/56F8027 64-Pin LQFP Mechanical Information Please see www.freescale.com for the most current case outline. Freescale Semiconductor 4X 16 TIPS 0 E1/2 E ( 0. ( VIEW AA BASE METAL PLATING b 0.08 C ...
Page 170
... Thermocouple temperature on top of package ( T = Thermal characterization parameter ( Power dissipation in package (W) D 170 , can be obtained from the equation C/W) . For instance, the user can change the size of the heat CA ) can be used to determine the junction temperature with C/W) 56F8037/56F8027 Data Sheet, Rev. 7 Freescale Semiconductor ...
Page 171
... Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the V and V circuits Freescale Semiconductor CAUTION of any voltages (GND) pin SS /V Ceramic and tantalum capacitors tend to provide better DDA SSA ...
Page 172
... V SS SSA and V traces. DDA SSA 2 C, the less than 0V. If positive in Ambient Temperature Order Number (MHz) Range 32 -40° 105° C MC56F8037VLH* 32 -40° 105° C MC56F8027VLH* 32 -40° 125° C MC56F8037MLH* 32 -40° 125° C MC56F8027MLH* Freescale Semiconductor are ...
Page 173
... Offset 0-7 Registers OFFST0-7 Power Control PWR ADPOWER Register Calibration Register CAL Control Register CTRL Timeout Register TOUT Counter Register CNTR Freescale Semiconductor Data Sheet Legacy New Acronym Acronym Analog-to-Digital Converter (ADC) Module ADCR1 ADC_CTRL1 ADC_ADCR1 ADCR2 ADC_CTRL2 ADC_ADCR2 ADZCC ADC_ZXCTRL ...
Page 174
... I2CTAR I2C_TAR I2CSAR I2C_SAR I2C_DATACMD I2C_SS_SCLHCNT I2C_SS_SCLLCNT I2C_FS_SCLHCNT I2C_FS_SCLLCNT I2C_INTRSTAT I2C_INTRMASK I2C_RAW_INTRSTAT I2C_RXTL I2C_TXTL I2C_CLRINTR I2C_CLR_RXUNDER I2C_CLROVER I2C_CLR_TXOVER I2C_CLR_RDREQ I2C_CLR_TXABRT Freescale Semiconductor Memory Address End 0xF280 0xF282 0xF242 0xF288 0xF28A 0xF28C 0xF28E 0xF290 0xF296 0xF298 0xF29A 0xF29C 0xF29E 0xF2A0 0xF2A2 0xF2A4 ...
Page 175
... Oscillator Control OCTRL Register Clock Check Register CLKCHK Protection Register PROT Clock Divider Register CLKDIV Configuration CNFG Register Security High Half SECHI Register Freescale Semiconductor Data Sheet Legacy New Acronym Acronym I2C_CLR_RXDONE I2C_CLRACTIVITY I2C_CLR_STOPDET I2C_CLR_STAR_DET I2C_CLR_GENCALL I2C_ENABLE I2C_STAT I2C_TXFLR I2C_RXFLR I2C_TX_ABRTSRC ...
Page 176
... FMOPT1 FMTST_SIG (n=0) B (n=1) C (n=2) D (n=3) GPIO_x_PUR GPIOx_DR GPIO_x_DR GPIO_x_DDR GPIO_x_PER GPIOx_IAR GPIO_x_IAR GPIO_x_IENR GPIO_x_IPOLR GPIOx_IPR GPIO_x_IPR GPIO_x_IESR GPIO_x_PPMODE GPIO_x_RAWDATA GPIO_x_DRIVE Freescale Semiconductor Memory Address End 0xF404 0xF410 0xF413 0xF414 0xF418 0xF41B 0xF41D 0xF1n0 0xF1n1 0xF1n2 0xF1n3 0xF1n4 0xF1n5 0xF1n6 0xF1n7 ...
Page 177
... RFLG Receiver Interrupt RIER Enable Register Transmitter Flag TFLG Register Transmitter Interrupt TIER Enable Register. Transmitter Msg Abort TARQ Request Register Freescale Semiconductor Data Sheet Legacy New Acronym Acronym Pulse Width Modulator (PWM) Module PMCTL PWM_CTRL PWM_PMCTL PMFCTL PWM_FCTRL PWM_PMFCTL PMFSA ...
Page 178
... CANIDMR4-7 0xF81C CANRXFG 0xF82F CANTXFG 0xF830 LVICTRL LVISTATUS LVISR QSCI_SCIBR QSCI_SCICR QSCI_SCICR2 QSCI_SCISR QSCI_SCIDR QSPI_SPSCR QSPI_SPDSR QSPI_SPDRR QSPI_SPDTR Freescale Semiconductor Memory Address End 0XF809 0XF80A 0XF80B 0XF80D 0XF80E 0XF80F 0xF813 0xF817 0xF81B 0xF81F 0xF820 0xF83F 0xF140 0xF141 0xF2n0 0xF2n1 0xF2n2 ...
Page 179
... Freescale Semiconductor 56F8037/56F8027 Data Sheet, Rev. 7 Electrical Design Considerations 179 ...
Page 180
... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® ...