MC56F8037VLH Freescale Semiconductor, MC56F8037VLH Datasheet - Page 107

• Manufacturer Part Number: MC56F8037VLH
• Description: IC DSP 16BIT DUAL 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8037VLH

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• Package: 64LQFP
• Family Name: 56F8xxx
• Maximum Speed: 32 MHz
• On-chip Adc: 2(8-chx10-bit)
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 5
• For Use With: MC56F8037EVM - BOARD EVAL FOR MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.3.11.3
6.3.11.4
6.3.11.5
This bit field is reserved. It must be set to 0.
6.3.11.6
6.3.11.7
This bit field is reserved. Each bit must be set to 0.
6.3.11.8
6.3.11.9
6.3.11.10 QSCI0 Clock Stop Disable (QSCI0_SD)—Bit 4
6.3.11.11 QSPI1 Clock Stop Disable (QSPI1_SD)—Bit 3
6.3.11.12 QSPI0 Clock Stop Disable (QSPI0_SD)—Bit 2
Each bit controls clocks to the indicated peripheral.
Freescale Semiconductor
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0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
Digital-to-Analog Converter 1 Clock Stop Disable (DAC1_SD)—Bit 13
Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)—Bit 12
Reserved—Bit 11
Analog-to-Digital Converter Clock Stop Disable (ADC_SD)—Bit 10
Reserved—Bits 9–7
Inter-Integrated Circuit Clock Stop Disable (I2C_SD)—Bit 6
QSCI1 Clock Stop Disable (QSCI1_SD)—Bit 5
56F8037/56F8027 Data Sheet, Rev. 7
Register Descriptions
107